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| intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet the intel ? lxt972m single-port 10/100 mbps phy tr ansceiver is an ieee compliant fast ethernet phy transceiver that directly supports both 100base-tx and 10base-t applications. it provides a media independent interface (mii) for easy attachment to 10/100 media access controllers (macs). both full and half-duplex operation at 10 mbps and 100 mbps is supported. operation mode can be set to auto-negotiation, para llel detection, or manual control. the device is powered from a single 3.3v power supply. applications product features combination 10base-t/100base-tx network interface cards (nics) wireless access points network printers 10/100 personal computer memory card international association (pcmcia) cards cable modems and set-top boxes 3.3v operation ieee 802.3-compliant 10base-t or 100base-tx with integrated filters auto-negotiation and parallel detection mii interface with extended register capability robust baseline wander correction carrier sense multiple access / collision detection (csma/cd) or full-duplex operation jtag boundary scan mdio serial port or hardware pin configurable integrated, programmable led drivers 48-pin low-profile quad flat package document number: 302875-005 revision date: 27-oct-2005 tx_en rx_er crs power supply management / mode select logic addr[1:0] mdio mdc rx_dv tpon tpop tpin tpip refclk/xi vcc gnd col rx_clk tx_clk txd[3:0] decoder & descrambler + - serial-to- parallel converter scrambler & encoder parallel/serial converter carrier sense data valid error detect auto negotiation manchester decoder manchester encoder 10 100 10 100 media select tp driver tp out register set register set clock generator + - 10bt collision detect clock generator osp adaptive eq with baseline wander cancellation osp slicer osp pulse shaper rxd[3:0] + - 100tx tp in rx pcs jtag 5 tdo tms tck trst_l reset_l b3387-13 led/cfg[3:1] tdi tx pcs xo
intel ? lxt972m single-port 10/100 mbps phy transceiver 2 datasheet document number: 302875-005 revision date: 27-oct-2005 information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. intel may make changes to specifications and product descriptions at any time, without notice. the intel ? lxt972m single-port 10/100 mbps phy transceiver may contain design defects or errors known as errata which may cause the produ ct to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com. intel and the intel logo are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states and other countries. *other names and brands may be claimed as the property of others. copyright ? 2005, intel corporation. intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 3 document number: 302875-005 revision date: 27-oct-2005 contents 1.0 introduction to this document .........................................................................................10 1.1 document overview ............................................................................................10 1.2 related documents.............................................................................................10 2.0 block diagram for intel ? lxt972m transceiver...............................................................11 3.0 pin assignments for intel ? lxt972m transceiver ...........................................................12 4.0 signal descriptions for intel ? lxt972m transceiver ....................................................... 15 5.0 functional description...................................................................................................... 21 5.1 device overview .................................................................................................22 5.1.1 comprehensive functionality ................................................................. 22 5.1.2 optimal signal processing architecture ................................................. 22 5.2 network media / protocol support.......................................................................23 5.2.1 10/100 network interface .......................................................................23 5.2.2 mii data interface...................................................................................25 5.2.3 configuration management interface ..................................................... 25 5.3 operating requirements .....................................................................................28 5.3.1 power requirements ..............................................................................28 5.3.2 clock requirements ............................................................................... 28 5.4 initialization..........................................................................................................29 5.4.1 mdio control mode and hardware control mode .................................31 5.4.2 reduced-power modes .......................................................................... 31 5.4.3 reset for intel ? lxt972m transceiver...................................................31 5.4.4 hardware configuration settings ...........................................................33 5.5 establishing link .................................................................................................34 5.5.1 auto-negotiation.....................................................................................34 5.5.2 parallel detection ...................................................................................35 5.6 mii operation.......................................................................................................36 5.6.1 mii clocks...............................................................................................37 5.6.2 transmit enable .....................................................................................38 5.6.3 receive data valid.................................................................................38 5.6.4 carrier sense .........................................................................................39 5.6.5 error signals...........................................................................................39 5.6.6 collision..................................................................................................39 5.6.7 loopback................................................................................................ 40 5.7 100 mbps operation............................................................................................41 5.7.1 100base-x network operations ...........................................................41 5.7.2 collision indication .................................................................................44 5.7.3 100base-x protocol sublayer operations ............................................45 5.8 10 mbps operation..............................................................................................50 5.8.1 10base-t preamble handling...............................................................50 5.8.2 10base-t carrier sense .......................................................................50 5.8.3 10base-t dribble bits ...........................................................................50 5.8.4 10base-t link integrity test .................................................................51 5.8.5 link failure.............................................................................................51 intel ? lxt972m single-port 10/100 mbps phy transceiver 4 datasheet document number: 302875-005 revision date: 27-oct-2005 5.8.6 10base-t sqe (heartbeat) .................................................................. 51 5.8.7 10base-t jabber .................................................................................. 51 5.8.8 10base-t polarity correction................................................................ 51 5.9 monitoring operations .........................................................................................52 5.9.1 monitoring auto-negotiation................................................................... 52 5.9.2 monitoring next page exchange............................................................ 52 5.9.3 led functions........................................................................................ 53 5.9.4 led pulse stretching ............................................................................. 54 5.10 boundary scan (jtag 1149.1) functions .......................................................... 55 5.10.1 boundary scan interface........................................................................ 55 5.10.2 state machine ........................................................................................ 55 5.10.3 instruction register ................................................................................ 55 5.10.4 boundary scan register ........................................................................ 56 5.10.5 device id register ................................................................................. 56 6.0 application information..................................................................................................... 57 6.1 magnetics information .........................................................................................57 6.2 typical twisted-pair interface............................................................................. 57 7.0 electrical specifications ................................................................................................... 61 7.1 electrical parameters .......................................................................................... 61 7.2 timing diagrams ................................................................................................. 65 8.0 register definitions - ieee base registers ..................................................................... 75 9.0 register definitions - product-specific registers ............................................................ 83 10.0 intel ? lxt972m transceiver package specifications...................................................... 90 10.1 top label markings............................................................................................. 91 11.0 product ordering information........................................................................................... 92 figures 1 intel ? lxt972m transceiver block diagram....................................................... 11 2 pin assignments for intel ? lxt972m transceiver 48-pin lqfp package ......... 12 3 management interface read frame structure ................................................... 27 4 management interface write frame structure ................................................... 27 5 initialization sequence for intel ? lxt972m transceiver ..................................... 30 6 link establishment overview)............................................................................. 34 7 clocking for 10base-t ...................................................................................... 37 8 clocking for 100base-x .................................................................................... 37 9 clocking for link down clock transition ............................................................ 38 10 intel ? lxt972m transceiver loopback paths .................................................... 40 11 100base-x frame format ................................................................................ 41 12 100base-tx data path ..................................................................................... 42 13 100base-tx reception with no errors ............................................................. 43 14 100base-tx reception with invalid symbol ..................................................... 43 15 100base-tx transmission with no errors ........................................................44 intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 5 document number: 302875-005 revision date: 27-oct-2005 16 100base-tx transmission with collision ..........................................................44 17 intel ? lxt972m protocol sublayers.................................................................... 45 18 led pulse stretching .........................................................................................54 19 intel ? lxt972m transceiver typical twisted-pair interface - switch ................. 58 20 intel ? lxt972m transceiver typical twisted-pair interface - nic .....................59 21 intel ? lxt972m transceiver typical media independent interface .................... 60 22 intel ? lxt972m transceiver 100base-tx receive timing ............................... 65 23 intel ? lxt972m transceiver 100base-tx transmit timing .............................. 66 24 intel ? lxt972m transceiver 10base-t receive timing ................................... 67 25 intel ? lxt972m transceiver 10base-t transmit timing .................................. 68 26 intel ? lxt972m transceiver 10base-t jabber and unjabber timing............... 69 27 intel ? lxt972m transceiver 10base-t sqe (heartbeat) timing...................... 70 28 intel ? lxt972m transceiver auto-negotiation and fast link pulse timing .......71 29 intel ? lxt972m transceiver fast link pulse timing.......................................... 71 30 intel ? lxt972m transceiver mdio input timing ................................................ 72 31 intel ? lxt972m transceiver mdio output timing .............................................72 32 intel ? lxt972m transceiver power-up timing .................................................. 73 33 intel ? lxt972m transceiver reset _l pulse width and recovery timing .......74 34 phy identifier bit mapping ................................................................................. 78 35 intel ? lxt972m transceiver lqfp package specifications............................... 90 36 sample lqfp package - intel ? lxt972m transceiver ...................................... 91 37 sample pb-free (rohs-compliant) lqfp package - intel ? lx972m transceiver 91 38 order matrix for intel ? lxt972m transceiver ..................................................... 92 tables 1 related documents from intel.............................................................................10 2 intel ? lxt972m transceiver signal types ......................................................... 13 3 intel ? lxt972m transceiver lqfp numeric pin list.......................................... 13 4 intel ? lxt972m transceiver mii data interface signal descriptions.................. 16 5 intel ? lxt972m transceiver mii controller interface signal descriptions .......... 17 6 intel ? lxt972m transceiver network interface signal descriptions .................. 17 7 intel ? lxt972m transceiver standard bus and interface signal descriptions... 17 8 intel ? lxt972m transceiver configuration and led driver signal descriptions 18 9 intel ? lxt972m transceiver power, ground, no-connect signal descriptions . 19 10 intel ? lxt972m transceiver jtag test signal descriptions ............................. 19 11 intel ? lxt972m transceiver pin types and modes ........................................... 20 12 intel ? lxt972m transceiver - phy device address selections......................... 26 13 hardware configuration settings for intel ? lxt972m transceiver .....................33 14 carrier sense, loopback, and collision conditions ............................................ 39 15 4b/5b coding ......................................................................................................46 16 valid jtag instructions.......................................................................................55 17 bsr mode of operation ...................................................................................... 56 18 device id register for intel ? lxt972m transceiver ...........................................56 19 magnetics requirements.....................................................................................57 20 i/o pin comparison of nic and switch rj-45 setups ........................................57 21 absolute maximum ratings for intel ? lxt972m transceiver .............................61 22 recommended operating conditions for intel ? lxt972m transceiver..............61 intel ? lxt972m single-port 10/100 mbps phy transceiver 6 datasheet document number: 302875-005 revision date: 27-oct-2005 23 digital i/o characteristics (except for mii, xi/xo, and led/cfg pins) .............. 62 24 digital i/o characteristics 1 - mii pins .................................................................. 62 25 i/o characteristics - refclk/xi and xo pins.................................................... 63 26 i/o characteristics - led/cfg pins ....................................................................63 27 100base-tx transceiver characteristics .......................................................... 64 28 10base-t transceiver characteristics...............................................................64 29 10base-t link integrity timing characteristics .................................................64 30 intel ? lxt972m transceiver 100base-tx receive timing parameters ...........65 31 intel ? lxt972m transceiver 100base-tx transmit timing parameters ......... 66 32 intel ? lxt972m transceiver 10base-t receive timing ................................... 67 33 intel ? lxt972m transceiver 10base-t transmit timing .................................. 68 34 intel ? lxt972m transceiver 10base-t jabber and unj abber timing............... 69 35 intel ? lxt972m transceiver 10base-t sqe (heart beat) timing ..................... 70 36 intel ? lxt972m transceiver auto-negotiation / fast link pulse timing............ 71 37 intel ? lxt972m transceiver mdio timing......................................................... 72 38 intel ? lxt972m transceiver power-up timing .................................................. 73 39 intel ? lxt972m transceiver reset_l pulse width and recovery timing ....... 74 40 register set for ieee base registers................................................................. 75 41 control register - address 0, hex 0 ................................................................... 76 42 mii status register #1 - address 1, hex 1.......................................................... 77 43 phy identification register 1 - address 2, hex 2 ............................................... 78 44 phy identification register 2 - address 3, hex 3 ............................................... 78 45 auto-negotiation advertisement register - address 4, hex 4 ............................ 79 46 auto-negotiation link partner base p age ability register - address 5, hex 5... 80 47 auto-negotiation expansion - address 6, hex 6 ................................................. 81 48 auto-negotiation next page transmit register - address 7, hex 7 ................... 82 49 auto-negotiation link partner next page receive register - address 8, hex 8 82 50 register set for product-specific registers ........................................................83 51 configuration register - address 16, hex 10...................................................... 84 52 status register #2 - address 17, hex 11............................................................ 85 53 status change register - address 19, hex 13 ................................................... 86 54 led configuration register - address 20, hex 14.............................................. 87 55 digital configuration register - address 26, hex 1a ..........................................88 56 transmit control register - address 30, hex 1e ................................................ 89 57 product ordering information .............................................................................. 92 intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 7 document number: 302875-005 revision date: 27-oct-2005 revision history intel ? lxt972m transceiver datasheet revision 005 revision date: 27-oct-2005 page description 91 added figure 36 ?sample lqfp package - intel? lxt972m transceiver? and figure 37 ?sample pb-free (rohs-compliant) lqfp package - intel? lx972m transceiver? under section 10.1, ?top label markings? . 92 modified table 57 ?product ordering information? : added rohs information 92 modified figure 38 ?order matrix for intel? lxt972m transceiver? . intel ? lxt972m transceiver datasheet revision 004 revision date: february 18, 2005 page description - removed ?preliminary? label from document. 10 added table 1 ?related documents from intel? 92 change to product ordering information in chapter 11.0, ?product ordering information? . intel ? lxt972m transceiver datasheet revision 003 revision date: october 21, 2004 page description 1 block diagram changed. 11 chapter 2.0, ?block diagram for intel? lxt972m transceiver? . block diagram changed. 12 chapter 3.0, ?pin assignments for intel? lxt972m transceiver? . - figure 2 ?pin assignments for intel? lxt972m transceiver 48-pin lqfp package? changed. - figure 11 ?pin assignments for intel ? lxt972m transceiver pb-free 48-pin lqfp? . added new figure for lead-free package. - table 2 ?intel? lxt972m transceiver signal types? . changed old table 2 to table 1 and table text changed. - table 3 ?intel? lxt972m transceiver lqfp numeric pin list? changed. 15 chapter 4.0, ?signal descriptions for intel? lxt972m transceiver? . - table 6 ?intel? lxt972m transceiver network interface signal descriptions? changed. - table 8 ?intel? lxt972m transceiver configuration and led driver signal descriptions? changed. 33 section 5.4.4, ?hardware configuration settings? . - text changed. - table 13 ?hardware configuration settings for intel? lxt972m transceiver? changed. 35 section 5.5.1.3, ?controlling auto-negotiation? . added text. 53 section 5.9.3, ?led functions? . text changed. 61 chapter 7.0, ?electrical specifications? . - table 20 ?absolute maximum ratings for intel ? lxt972m transceiver? changed. - table 23 ?digital i/o characteristics (except for mii, xi/xo, and led/cfg pins)? changed. - table 27 ?100base-tx transceiver characteristics? changed. 66 section 7.2, ?timing diagrams? . added timing diagrams. intel ? lxt972m single-port 10/100 mbps phy transceiver 8 datasheet document number: 302875-005 revision date: 27-oct-2005 75 chapter 8.0, ?register definitions - ieee base registers? - table 40 ?register set for ieee base registers? changed. - table 41 ?control register - address 0, hex 0? changed. 83 chapter 9.0, ?register definitions - product-specific registers? . - table 50 ?register set for product-specific registers? changed. - table 54 ?led configuration register - address 20, hex 14? changed. - table 56 ?transmit control register - address 30, hex 1e? 90 chapter 10.0, ?intel? lxt972m transceiver package specifications? . - figure 35 ?intel? lxt972m transceiver lqfp package specifications? changed. intel ? lxt972m transceiver datasheet revision 002 revision date: july 14, 2004 page description 1 text changed. 10 figure 1 ?intel ? lxt972m transceiver block diagram? - deleted ecl driver from figure. 21 section 5.1, ?introduction? - text changed. 22 section 5.2.1.1, ?twisted-pair interface? - added text on mdi crossover. 23 section 5.2.1.2, ?fault detection and reporting? - text changed. 26 section 5.3.2.1, ?external crystal/oscillator? - text changed. 30 table 12 ?hardware configuration settings for intel ? lxt972m transceiver? - bit value for 0.8 changed. 33 section 5.5.2, ?parallel detection? - text changed. 36 section 5.6.2, ?transmit enable? - text changed. 37 section 5.6.4, ?carrier sense? - text changed. 45 section 5.7.3.1.1, ?preamble handling? - text changed. 47 section 5.7.3.2.1, ?link? - added text. 47 section 5.7.3.2.2, ?link failure override? - added text. 47 section 5.7.3.2.4, ?receive data valid? - text changed. 48 section 5.7.3.3.2, ?polarity correction? - text changed. 53 section 5.9.4, ?led pulse stretching? - text changed. 80 table 46 ?auto-negotiation next page transmit register - address 7, hex 7? - bits 7.10:0 and 7.13 changed. 80 table 47 ?auto-negotiation link partner next page receive register - address 8, hex 8? - bits 8.18 and 8.10:0 changed. 85 table 52 ?led configuration register - address 20, hex 14? - bit 20.0 changed. intel ? lxt972m transceiver datasheet revision 001 revision date: july 2, 2004 page description - initial release of this document. intel ? lxt972m transceiver datasheet revision 003 revision date: october 21, 2004 page description intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 9 document number: 302875-005 revision date: 27-oct-2005 intel ? lxt972m single-port 10/100 mbps phy transceiver 10 datasheet document number: 302875-005 revision date: 27-oct-2005 1.0 introduction to this document this document includes information on the intel ? lxt972m single-port 10/100 mbps phy transceiver (called hereafter the lxt972m transceiver) 1.1 document overview this document includes the following subjects: ? chapter 2.0, ?block diagram for intel? lxt972m transceiver? ? chapter 3.0, ?pin assignments for intel? lxt972m transceiver? ? chapter 4.0, ?signal descriptions for intel ? lxt972m transceiver? ? chapter 5.0, ?functional description? ? chapter 6.0, ?application information? ? chapter 7.0, ?electrical specifications? ? chapter 8.0, ?register definitions - ieee base registers? ? chapter 9.0, ?register definitions - product-specific registers? ? chapter 10.0, ?intel? lxt972m transceiver package specifications? ? chapter 11.0, ?product ordering information? 1.2 related documents table 1. related documents from intel document title document number intel ? lxt971a , lxt972a , lxt972m single-port 10/100 mbps phy transceivers specification update 249354 intel ? lxt971a, lxt972a, and lxt972m 3.3v phy transceivers design and layout guide - application note 249016 magnetic manufacturers for networking product applications - application note 248991 intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 11 document number: 302875-005 revision date: 27-oct-2005 2.0 block diagram for intel ? lxt972m transceiver figure 1 is a block diagram of the lxt972m transceiver. (this block diagram is the same as the block diagram on the first page of this document. this copy of the block diagram appears here as a convenience to the reader.) figure 1. intel ? lxt972m transceiver block diagram tx_en rx_er crs power supply management / mode select logic addr[1:0] mdio mdc rx_dv tpon tpop tpin tpip refclk/xi vcc gnd col rx_clk tx_clk txd[3:0] decoder & descrambler + - serial-to- parallel converter scrambler & encoder parallel/serial converter carrier sense data valid error detect auto negotiation manchester decoder manchester encoder 10 100 10 100 media select tp driver tp out register set register set clock generator + - 10bt collision detect clock generator osp adaptive eq with baseline wander cancellation osp slicer osp pulse shaper rxd[3:0] + - 100tx tp in rx pcs jtag 5 tdo tms tck trst_l reset_l b3387-13 led/cfg[3:1] tdi tx pcs xo intel ? lxt972m single-port 10/100 mbps phy transceiver 12 datasheet document number: 302875-005 revision date: 27-oct-2005 3.0 pin assignments for intel ? lxt972m transceiver figure 2 shows the pin assignments for the lxt972m transceiver lqfp package. figure 2. pin assignments for intel ? lxt972m transceiver 48-pin lqfp package b3814-02 1 2 3 4 5 6 7 8 9 10 11 12 crs r efclk/x1 x0 reset_l gnd vccio nc nc gnd addr0 addr1 rbias gnda tpop tpon vcca tpip tpin tdi tdo tms tck trst_l gnd col txd3 txd2 txd1 txd0 tx_en tx_clk rx_er rx_clk vccd nc nc 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 37 38 39 40 41 42 43 44 45 46 47 48 nc rxd1 rxd2 rxd3 mdc mdio gnd vccio led/cfg 1 led/cfg 2 led/cfg 3 gnd dj972m a4 xxxxxxxx 'y y year pin 1 fpo number c m part number revision number intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 13 document number: 302875-005 revision date: 27-oct-2005 note: for the tables in this section and the following sections, the abbreviations listed in table 2 are used for the ?type? column. table 3 lists the lxt972m transceiver lqfp pin numbers, symbols, and pin types. ta ble 2 . intel ? lxt972m transceiver signal types abbreviation meaning ai analog input ao analog output i input i/o input/output o output od open drain ta ble 3 . intel ? lxt972m transceiver lqfp numeric pin list (sheet 1 of 2) pin symbol type 1 crs o 2 refclk/xi ai 3xo ao 4 reset_l i 5gnd ? 6 vccio ? 7nc ? 8nc ? 9gnd ? 10 addr0 i 11 addr1 i 12 rbias ai 13 gnda ? 14 tpop ao 15 tpon ao 16 vcca ? 17 tpip ai 18 tpin ai 19 tdi i 20 tdo o 21 tms i 22 tck i 23 trst_l i 24 gnd ? 25 gnd ? intel ? lxt972m single-port 10/100 mbps phy transceiver 14 datasheet document number: 302875-005 revision date: 27-oct-2005 26 led/cfg3 i/o 27 led/cfg2 i/o 28 led/cfg1 i/o 29 vccio ? 30 gnd ? 31 mdio i/o 32 mdc i 33 rxd3 o 34 rxd2 o 35 rxd1 o 36 rxd0 o 37 rx_dv o 38 gnd ? 39 vccd ? 40 rx_clk o 41 rx_er o 42 tx_clk o 43 tx_en i 44 txd0 i 45 txd1 i 46 txd2 i 47 txd3 i 48 col o table 3. intel ? lxt972m transceiver lqfp numeric pin list (sheet 2 of 2) pin symbol type intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 15 document number: 302875-005 revision date: 27-oct-2005 4.0 signal descriptions for intel ? lxt972m transceiver intel recommends the following configurations for unused pins: ? unused inputs. configure all unused inputs and unused multi-function pins for inactive states. ? unused outputs. leave all unused outputs floating. ? no connects. do not use pins designated as nc (no connect), and do not terminate them. note: for the tables in this section, the abbreviations listed in table 2, ?intel? lxt972m transceiver signal types? on page 13 are used for the ?type? column. tables in this section include the following ? table 4, ?intel? lxt972m transceiver mii data interface signal descriptions? ? table 5, ?intel? lxt972m transceiver mii controller interface signal descriptions? ? table 6, ?intel? lxt972m transceiver network interface signal descriptions? ? table 7, ?intel? lxt972m transceiver standard bus and interface signal descriptions? ? table 8, ?intel? lxt972m transceiver configuration and led driver signal descriptions? ? table 9, ?intel? lxt972m transceiver power, ground, no-connect signal descriptions? ? table 10, ?intel? lxt972m transceiver jtag test signal descriptions? ? table 11, ?intel? lxt972m transceiver pin types and modes? intel ? lxt972m single-port 10/100 mbps phy transceiver 16 datasheet document number: 302875-005 revision date: 27-oct-2005 table 4 lists signal descriptions of the lxt972m transceiver mii data interface pins. table 4. intel ? lxt972m transceiver mii data interface signal descriptions lqfp pin# symbol type signal description 47 46 45 44 txd3 txd2 txd1 txd0 i transmit data. txd is a group of parallel data signals that are driven by the mac. txd[3:0] transition synchronously with respect to tx_clk. txd[0] is the least-significant bit. 43 tx_en i transmit enable. the mac asserts this signal when it drives valid data on txd. this signal must be synchronized to tx_clk. 42 tx_clk o transmit clock. tx_clk is sourced by the phy in both 10 and 100 mbps operations. 2.5 mhz for 10 mbps operation 25 mhz for 100 mbps operation. 33 34 35 36 rxd3 rxd2 rxd1 rxd0 o receive data. rxd is a group of parallel signals that transition synchronously with respect to rx_clk. rxd[0] is the least-significant bit. 37 rx_dv o receive data valid. the lxt972m transceiver asserts this signal when it drives valid data on rxd. this output is synchronous to rx_clk. 41 rx_er o receive error. signals a receive error condition has occurred. this output is synchronous to rx_clk. 40 rx_clk o receive clock. 25 mhz for 100 mbps operation. 2.5 mhz for 10 mbps operation. for details, see ?clock requirements? on page 28 in chapter 5.0, ?functional description? . 48 col o collision detected . the lxt972m transceiver asserts this output when a collision is detected. this output remains high for the duration of the collision. this signal is asynchronous and is inactive during full- duplex operation. 1 crs o carrier sense . during half-duplex operation (register bit 0.8 = 0), the lxt972m transceiver asserts this output when either transmitting or receiving data packets. during full-duplex operation (register bit 0.8 = 1), crs is asserted only during receive. crs assertion is asynchronous with respect to rx_clk. crs is de-asserted on loss of carrier, synchronous to rx_clk. intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 17 document number: 302875-005 revision date: 27-oct-2005 table 5 lists signal descriptions of the lxt972m transceiver mii controller interface pins. table 6 lists signal descriptions of the lxt972m transceiver network interface pins. table 7 lists signal descriptions of the lxt972m transceiver standard bus and interface signals. ta ble 5 . intel ? lxt972m transceiver mii controller interface signal descriptions lqfp pin# symbol type signal description 32 mdc i management data clock . clock for the mdio serial data channel. maximum frequency is 8 mhz. 31 mdio i/o management data input/output . bidirectional serial data channel for phy/sta communication. ta ble 6 . intel ? lxt972m transceiver network interface signal descriptions lqfp pin# symbol type signal description 14 15 tpop tpon ao twisted-pair outputs, positive and negative. during 100base-tx or 10base-t operation, tpop/n pins drive ieee 802.3 compliant pulses onto the line. 17 18 tpip tpin ai twisted-pair inputs, positive and negative. during 100base-tx or 10base-t operation, tpip/n pins receive differential 100base-tx or 10base-t signals from the line. ta ble 7 . intel ? lxt972m transceiver standard bus and interface signal descriptions lqfp pin# symbol type signal description 10 11 addr0 addr1 i address . set device address. intel ? lxt972m single-port 10/100 mbps phy transceiver 18 datasheet document number: 302875-005 revision date: 27-oct-2005 table 8 lists signal descriptions of the lxt972m transceiver configuration and led driver pins. note: pull-up/pull-down resistors of 10k ohms can be implemented if leds are not used in the design. table 8. intel ? lxt972m transceiver configuration and led driver signal descriptions lqfp pin# symbol type signal description 4 reset_l i reset . this active low input is ored with the control register reset bit (register bit 0.15). the lxt972m transceiver reset cycle is extended to 258 s (nominal) after reset is de-asserted. 12 rbias ai reference current bias . this pin provides bias current for the internal circuitry. must be tied to ground through a 22.1 k , 1% resistor. 2 3 refclk/xi xo ai and ao reference clock input / crystal input and crystal output . a 25 mhz crystal oscillator circuit can be connected across xi and xo. a clock can also be used at xi. refer to section 5.3.2, ?clock requirements? on page 28 in the functional description section. 26 27 28 led/cfg3 led/cfg2 ledcfg1 i/o led drivers 1-3. these pins drive led indicators. each led can display one of several available status conditions as selected by the led configuration register. (for details, see tab le 5 4, ?led configuration register - address 20, hex 14? on page 87 .) configuration inputs 1-3. these pins also provide initial configuration settings. (for details, see table 13, ?hardware configuration settings for intel? lxt972m transceiver? on page 33.) intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 19 document number: 302875-005 revision date: 27-oct-2005 table 9 lists signal descriptions of the lxt972m transceiver power, ground, and no-connect pins. table 10 lists signal descriptions of lxt972m transceiver joint test action group (jtag) pins. note: if a jtag port is not used, these pins do not need to be terminated. ta ble 9 . intel ? lxt972m transceiver power, ground, no-connect signal descriptions lqfp pin# symbol type signal description 13 gnda ? analog ground. 5, 9, 24, 25, 30, 38 gnd ? ground input/output. ground return for digital i/o circuits (vccio). 6, 29 vccio ? mii power. requires either a 3.3 v or a 2.5 v supply. must be supplied from the same source used to power the mac on the other side of the mii. for the lxt972m transceiver, vccio is 3.3 v. 16 vcca ? analog power. requires a 3.3 v power supply. 39 vccd ? digital power. requires a 3.3 v power supply. 7, 8 nc ? no connection . these pins are not used and must not be terminated. ta ble 1 0. intel ? lxt972m transceiver jtag test signal descriptions lqfp pin# symbol type signal description 19 tdi i test data input . test data sampled with respect to the rising edge of tck. 20 tdo o test data output . test data driven with respect to the falling edge of tck. 21 tms i test mode select . 22 tck i test clock . clock input for boundary scan. 23 trst_l i test reset . this active-low test reset input is sourced by ate. intel ? lxt972m single-port 10/100 mbps phy transceiver 20 datasheet document number: 302875-005 revision date: 27-oct-2005 table 11 lists pin types and modes of the lxt972m transceiver. note: ? dh = driven high (logic 1) ? dl = driven low (logic 0) ? hz = high impedance ? id = internal pull-down (weak) table 11. inte l ? lxt972m transceiver pin types and modes modes rxd3:0 rx_dv tx/rx clks output rx_er output col output crs output txd3:0 input tx_en input hwreset dl dl dh dl dl dl id id sftpwrdn dl dl active dl dl dl id id isolate hz with id hz with id hz with id hz with id hz with id hz with id id id intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 21 document number: 302875-005 revision date: 27-oct-2005 5.0 functional description this chapter has the following sections: ? section 5.1, ?device overview? ? section 5.2, ?network media / protocol support? ? section 5.3, ?operating requirements? ? section 5.4, ?initialization? ? section 5.5, ?establishing link? ? section 5.6, ?mii operation? ? section 5.7, ?100 mbps operation? ? section 5.8, ?10 mbps operation? ? section 5.9, ?monitoring operations? ? section 5.10, ?boundary scan (jtag 1149.1) functions? intel ? lxt972m single-port 10/100 mbps phy transceiver 22 datasheet document number: 302875-005 revision date: 27-oct-2005 5.1 device overview the lxt972m transceiver is a single-port fast ethernet 10/100 transceiver that supports 10 mbps and 100 mbps networks. it complies with applicable requirements of ieee 802.3. it directly drives either a 100base-tx line or a 10base-t line. 5.1.1 comprehensive functionality the lxt972m transceiver provides a standard media independent interface (mii) for 10/100 macs. the lxt972m transceiver performs all functions of the physical coding sublayer (pcs) and physical media attachment (pma) sublayer as defined in the ieee 802.3 100base-x standard. it also performs all functions of the physical media dependent (pmd) sublayer for 100base-tx connections. if the lxt972m transceiver is not set for forced operation, it uses auto-negotiation/parallel detection to automatically determine line operating conditions. if the phy device on the other side of the link supports auto-negotiation, the lxt972m transceiver auto-negotiates with it using fast link pulse (flp) bursts. if the phy partner does not support auto-negotiation, the lxt972m transceiver automatically detects the presence of either link pulses (10 mbps phy) or idle symbols (100 mbps phy) and sets its operating conditions accordingly. the lxt972m transceiver provides half-duplex and full-duplex operation at 100 mbps and 10 mbps. 5.1.2 optimal signal processing architecture the lxt972m transceiver incorporates high-efficiency optimal signal processing (osp) design techniques, which combine optimal properties of digital and analog signal processing. the receiver utilizes decision feedback equalization to increase noise and cross-talk immunity by as much as 3 db over an ideal all-analog equalizer. using osp mixed-signal processing techniques in the receive equalizer avoids the quantization noise and calculation truncation errors found in traditional dsp-based receivers (typically complex dsp engines with a/d converters). this results in improved receiver noise and cross-talk performance. the osp signal processing scheme also requires substantially less computational logic than traditional dsp-based designs. this lowers power consumption and also reduces the logic switching noise generated by dsp engines. this logic switching noise can be a considerable source of emi generated on the device?s power supplies. the osp-based lxt972m transceiver provides improved data recovery, emi performance, and low power consumption. intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 23 document number: 302875-005 revision date: 27-oct-2005 5.2 network media / protocol support this section includes the following: ? section 5.2.1, ?10/100 network interface? ? section 5.2.2, ?mii data interface? ? section 5.2.3, ?configuration management interface? the lxt972m transceiver supports both 10base-t and 100base-tx ethernet over twisted- pair. 5.2.1 10/100 network interface the network interface port consists of two differential signal pairs. for specific pin assignments, see chapter 4.0, ?signal descriptions for intel? lxt972m transceiver? . the lxt972m transceiver output drivers can generate one of the following outputs: ? 100base-tx ? 10base-t when not transmitting data, the lxt972m transceiver generates ieee 802.3-compliant link pulses or idle code. depending on the mode selected, input signals are decoded as one of the following: when not transmitting data, the lxt972m transceiver generates ieee 802.3-compliant link pulses or idle code. depending on the mode selected, input signals are decoded as one of the following: ? 100base-tx ? 10base-t auto-negotiation/parallel detection or manual control is used to determine the speed of this interface. intel ? lxt972m single-port 10/100 mbps phy transceiver 24 datasheet document number: 302875-005 revision date: 27-oct-2005 5.2.1.1 twisted-pair interface the lxt972m transceiver supports either 100base-tx or 10base-t connections over 100 , category 5, unshielded twisted pair (utp) cable. when operating at 100 mbps, the lxt972m transceiver continuously transmits and receives mlt3 symbols. when not transmitting data, the lxt972m transceiver generates ?idle? symbols. during 10 mbps operation, manchester-encoded data is exchanged. when no data is being exchanged, the line is left in an idle state. link pulses are transmitted periodically to keep the link up. only a transformer, rj-45 connector, load resistor, and bypass capacitors are required to complete this interface. on the transmit side, the lxt972m transceiver has an active internal termination and does not require external termination resistors. intel's patented waveshaping technology shapes the outgoing signal to help reduce the need for external emi filters. four slew rate settings allow the designer to match the output waveform to the magnetic characteristics. on the receive side, the internal impedance is high enough that it has no practical effect on the external termination circuit. (for the slew rate settings, see table 56, ?transmit control register - address 30, hex 1e? on page 89 .) note: on the lxt972m transceiver, mdix crossover (mdix) is supported by board design. 5.2.1.2 remote fault detection and reporting the lxt972m transceiver supports the remote fault detection and reporting mechanisms. ?remote fault? refers to a mac-to-mac communication function that is transparent to phy layer devices. it is used only during auto-negotiation, and is applicable only to twisted-pair links. remote fault detection. register bit 4.13 in the auto-negotiation advertisement register is reserved for remote fault indications. it is typically used when re-starting the auto-negotiation sequence to indicate to the link partner that the link is down because the advertising device detected a local fault. when the lxt972m transceiver receives a remote fault indication from its partner during auto- negotiation, the following occurs: ? register bit 5.13 in the link partner base page ability register is set. ? remote fault register bit 1.4 in the mii status register is set to pass this information to the local controller. intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 25 document number: 302875-005 revision date: 27-oct-2005 5.2.2 mii data interface the lxt972m transceiver supports a standard media independent interface (mii). the mii consists of a data interface and a management interface. the mii data interface passes data between the lxt972m transceiver and a media access controller (mac). separate parallel buses are provided for transmit and receive. this interface operates at either 10 mbps or 100 mbps. the speed is set automatically, once the operating conditions of the network link have been determined. for details, see section 5.6, ?mii operation? on page 36 . increased mii drive strength. a higher media independent interface (mii) drive strength may be desired in some designs to drive signals over longer pcb trace lengths, or over high-capacitive loads, through multiple vias, or through a connector. the mii drive strength in the lxt972m transceiver can be increased by setting register bit 26.11 through software control. setting register bit 26.11 = 1 through the mdc/mdio interface sets the mii pins (rxd[3:0], rx_dv, rx_clk, rx_er, col, crs, and tx_clk) to a higher drive strength. 5.2.3 configuration management interface the lxt972m transceiver provides both an mdio interface and a reduced hardware control interface for device configuration and management. 5.2.3.1 mdio management interface mdio management interface topics include the following: ? section 5.2.3.1.1, ?mdio addressing for intel? lxt972m transceiver? ? section 5.2.3.1.2, ?mdio frame structure? the lxt972m transceiver supports the ieee 802.3 mii management interface also known as the management data input/output (mdio) interface. this interface allows upper-layer devices to monitor and control the state of the lxt972m transceiver. the mdio interface consists of a physical connection, a specific protocol that runs across the connection, and an internal set of addressable registers. some registers are required and their functions are defined by the ieee 802.3 standard. the lxt972m transceiver also supports additional registers for expanded functionality. the lxt972m transceiver supports multiple internal registers, each of which is 16 bits wide. specific register bits are referenced using an ?x.y? notation, where x is the register number (0-31) and y is the bit number (0-15). 5.2.3.1.1 mdio addressing for intel ? lxt972m transceiver the mdio addressing protocol allows a controller to communicate with multiple lxt972m transceivers.as listed in table 12 , pins addr[1:0] determine the phy device address that is selected. intel ? lxt972m single-port 10/100 mbps phy transceiver 26 datasheet document number: 302875-005 revision date: 27-oct-2005 table 12. intel ? lxt972m transceiver - phy device address selections addr1 (pin 11) addr0 (pin 10) phy device address selected 00 0 01 1 10 28 11 29 intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 27 document number: 302875-005 revision date: 27-oct-2005 5.2.3.1.2 mdio frame structure the physical interface consists of a data line (mdio) and clock line (mdc). the frame structure is shown in figure 3 and figure 4 (read and write). mdio interface timing is given in chapter 7.0, ?electrical specifications?. 5.2.3.2 hardware control interface the lxt972m transceiver provides a hardware control interface for applications where the mdio is not desired. the hardware control interface uses the hardware configuration pins to set device configuration. for details, see section 5.4.4, ?hardware configuration settings? on page 33 . figure 3. management interface read frame structure figure 4. management interface write frame structure mdc mdio (read) 32 "1"s0110 preamble st op code phy address turn around z0 a4 a3 a0 r4 r3 r0 register address d15 d14 d1 data write read d15 d14 d1 d0 idle high z b3489-01 mdc mdio (write) 32 "1"s 0101 preamble st op code phy address turn around 1 0 a4 a3 a0 r4 r3 r0 register address d15 d14 d1 d0 data idle idle write b3490-01 intel ? lxt972m single-port 10/100 mbps phy transceiver 28 datasheet document number: 302875-005 revision date: 27-oct-2005 5.3 operating requirements 5.3.1 power requirements the lxt972m transceiver requires three power supply inputs: ? vcca ? vccd ? vccio the digital and analog circuits require 3.3 v supplies (vcca and vccd). these inputs may be supplied from a single source. each supply input must be de-coupled to ground. an additional supply may be used for the mii (vccio). the supply may be either +2.5 v or +3.3 v. also, the inputs on the mii interface are tolerant to 5 v signals from the controller on the other side of the mii interface. for mii i/o characteristics, see table 24, ?digital i/o characteristics1 - mii pins? on page 62 . note: bring up power supplies as close to the same time as possible. note: as a matter of good practice, keep power supplies as clean as possible. 5.3.2 clock requirements 5.3.2.1 external crystal/oscillator the lxt972m transceiver requires a reference clock input that is used to generate transmit signals and recover receive signals. it may be provided by either of two methods: by connecting a crystal across the oscillator pins (xi and xo) with load capacitors, or by connecting an external clock source to pin xi. the connection of a clock source to the xi pin requires the xo pin to be left open. to minimize transmit jitter, intel recommends a crystal-based clock instead of a derived clock (that is, a pll- based clock). a crystal is typically used in nic applications. an external 25 mhz clock source, rather than a crystal, is frequently used in switch applications. for clock timing requirements, see table 25, ?i/o characteristics - refclk/xi and xo pins? on page 63 . 5.3.2.2 mdio clock the mii management channel (mdio) also requires an external clock. the managed data clock (mdc) speed is a maximum of 8 mhz. for details, see table 37, ?intel? lxt972m transceiver mdio timing? on page 72 . intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 29 document number: 302875-005 revision date: 27-oct-2005 5.4 initialization this section includes the following topics: ? section 5.4.1, ?mdio control mode and hardware control mode? ? section 5.4.2, ?reduced-power modes? ? section 5.4.3, ?reset for intel? lxt972m transceiver? ? section 5.4.4, ?hardware configuration settings? when the lxt972m transceiver is first powered on, reset, or encounters a link failure state, it checks the mdio register configuration bits to determine the line speed and operating conditions to use for the network link. intel ? lxt972m single-port 10/100 mbps phy transceiver 30 datasheet document number: 302875-005 revision date: 27-oct-2005 figure 5 shows the initialization sequence for the lxt972m transceiver. the configuration bits may be set by the hardware control or mdio interface. figure 5. initialization sequence for intel ? lxt972m transceiver reset mdio registers to values read at h/w control interface at last hardware reset or power-up reset pass control to mdio interface power-up or reset initialize mdio registers read h/w control interface software reset? yes b3502-02 intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 31 document number: 302875-005 revision date: 27-oct-2005 5.4.1 mdio control mode and hardware control mode in the mdio control mode, the lxt972m transceiver reads the hardware control interface pins to set the initial (default) values of the mdio regi sters. once the initial values are set, bit control reverts to the mdio interface. the following modes are available using mdio control. ? force network link operation to: ? 100base-tx, full-duplex ? 100base-tx, half-duplex ? 10base-t, full-duplex ? 10base-t, half-duplex ? allow auto-negotiation/parallel-detection on power-up or hardware reset, the lxt972m transceiver reads the hardware control interface pins and sets the mdio registers accordingly. the following modes are available using the hardware control: ? auto-negotiation-enabled advertising, either: ? 10/100 base-t full/half duplex ? 10/100 base-t half duplex ? lxt972m transceiver device id enable ? link hold-off when the network link is forced to a specific configuration, the lxt972m transceiver immediately begins operating the network interface as commanded. when auto-negotiation is enabled, the lxt972mtransceiver begins the auto-negotiation/parallel-detection operation. 5.4.2 reduced-power modes this section discusses the lxt972m transceiver reduced-power modes. 5.4.2.1 software power down software power-down control is provided by register bit 0.11 in the control register. (see table 41 on page 76.) during soft power-down, the following conditions are true: ? the network port is shut down. ? the mdio registers remain accessible. 5.4.3 reset for intel ? lxt972m transceiver the lxt972m transceiver provides both hardware and software resets, each of which manage differently the configuration control of auto-negotiation, speed, and duplex-mode selection. for a software reset, register bit 0.15 = 1. for register bit definitions used for software reset, see table 41, ?control register - address 0, hex 0? on page 76 . intel ? lxt972m single-port 10/100 mbps phy transceiver 32 datasheet document number: 302875-005 revision date: 27-oct-2005 ? during a software reset, bit settings in table 45, ?auto-negotiation advertisement register - address 4, hex 4? on page 79 are not re-read from the lxt972m transceiver configuration pins. instead, the bit settings revert to the values that were read in during the last hardware reset. therefore, any changes to pin values made since the last hardware reset are not detected during a software reset. ? during a software reset, registers are available for reading. to see when the lxt972m transceiver has completed reset, the reset bit can be polled (that is, register bit 0.15 = 0). for pin settings used during a hardware reset, see section 5.4.4, ?hardware configuration settings? . during a hardware reset, configuration settings for auto-negotiation and speed are read in from pins, and register information is unavailable for 1 ms after de-assertion of the reset. intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 33 document number: 302875-005 revision date: 27-oct-2005 5.4.4 hardware configuration settings the lxt972m transceiver provides a hardware option to set the initial device configuration. as listed in table 13, the hardware option uses the hardware configuration pins, the settings for which provide control bits. table 13. hardware configuration settings for intel ? lxt972m transceiver desired mode led/cfg pin settings 1 resulting register bit values control register auto-negotiation advertisement register auto- neg. speed (mbps) duplex 123 auto- neg. 0.12 speed 0.13 full- duplex 0.8 100 base-tx full- duplex 4.8 100 base -tx 4.7 10 base-t full- duplex 4.6 10 base-t 4.5 disabled 10 half lll 0 00 n/a auto-negotiation advertisement full l l h 0 1 100 half l h l 1 0 full l h h 1 1 enabled 100 only half h l l 1 10 0 1 0 0 full/half h l h 1 1 1 1 0 0 10/100 half only h h l 1 0 0 1 0 1 full or half hhh 1 1 1 1 1 1 1. l = low, and h = high. for led/cfg pin assignments, see chapter 3.0, ?pin assignments for intel? lxt972m transceiver? . intel ? lxt972m single-port 10/100 mbps phy transceiver 34 datasheet document number: 302875-005 revision date: 27-oct-2005 5.5 establishing link figure 6 shows an overview of link establishment for the lxt972m transceiver. note: when a link is established by parallel detection, the lxt972m transceiver sets the duplex mode to half-duplex, as defined by the ieee 802.3 standard. 5.5.1 auto-negotiation if not configured for forced operation, the lxt972m transceiver attempts to auto-negotiate with its link partner by sending fast link pulse (flp) bursts. each burst consists of up to 33 link pulses spaced 62.5 s apart. odd link pulses (clock pulses) are always present. even link pulses (data pulses) may be absent or present to indicate a ?0? or a ?1?. each flp burst exchanges 16 bits of data, which are referred to as a ?link code word?. all devices that support auto-negotiation must implement the ?base page? defined by the ieee 802.3 standard (registers 4 and 5). the lxt972m transceiver also supports the optional ?next page? function as listed in table 48, ?auto-negotiation next page transmit register - address 7, hex 7? on page 82 and table 49, ?auto-negotiation link partner next page receive register - address 8, hex 8? on page 82 . 5.5.1.1 base page exchange by exchanging base pages, the lxt972m transceiver and its link partner communicate their capabilities to each other. both sides must receive at least three consecutive identical base pages for negotiation to continue. each side identifies the highest common capabilities that both sides support, and each side configures itself accordingly. figure 6. link establishment overview) check value 0.12 start done enable auto-neg/parallel detection go to forced settings attempt auto- negotiation listen for 10t link pulses listen for 100tx idle symbols link up? no yes power-up, reset, or link failure disable auto-negotiation 0.12 = 0 0.12 = 1 b3496-01 intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 35 document number: 302875-005 revision date: 27-oct-2005 5.5.1.2 manual next page exchange ?next page exchange? information is additional information that exceeds the information required by base page exchange and that is sent by ?next pages?. the lxt972m transceiver fully supports the ieee 802.3 standard method of negotiation through the next page exchange. the next page exchange uses register 7 to send information and register 8 to receive it. next page exchange occurs only if both ends of the link partners advertise their ability to exchange next pages. register bit 6.1 is used to make manual next page exchange easier for software. this register bit is cleared when a new negotiation occurs, preventing the user from reading an old value in register 6 and assuming there is valid information in registers 5 and 8. 5.5.1.3 controlling auto-negotiation when auto-negotiation is controlled by software, intel recommends the following steps: 1. after power-up, power-down, or reset, the power-down recovery time (specified in table 39, ?intel? lxt972m transceiver reset_l pulse width and recovery timing? on page 74 ) must be exhausted before proceeding. 2. set the auto-negotiation advertisement register bits in register 4 as desired. 3. enable auto-negotiation. (set mdio register bit 0.12 = 1.) 4. to ensure proper operation, enable or restart auto-negotiation as soon as possible after writing to register 4. 5.5.2 parallel detection in parallel with auto-negotiation, the lxt972m transceiver also monitors for 10 mbps normal link pulses (nlp) or 100 mbps idle symbols. if either symbol is detected, the device automatically reverts to the corresponding speed in half-duplex mode. parallel detection allows the lxt972m transceiver to communicate with devices that do not support auto-negotiation. when parallel detection resolves a link, the link must be established in half-duplex mode. according to ieee standards, the forced link partner cannot be configured to full-duplex. if the auto-negotiation link partner does not advertise half-duplex capability at the speed of the forced link partner, link is not established. the ieee standard prevents full-duplex-to-half-duplex link connections. intel ? lxt972m single-port 10/100 mbps phy transceiver 36 datasheet document number: 302875-005 revision date: 27-oct-2005 5.6 mii operation this section includes the following topics: ? section 5.6.1, ?mii clocks? ? section 5.6.2, ?transmit enable? ? section 5.6.3, ?receive data valid? ? section 5.6.4, ?carrier sense? ? section 5.6.5, ?error signals? ? section 5.6.6, ?collision? ? section 5.6.7, ?loopback? the lxt972m transceiver implements the media independent interface (mii) as defined by the ieee 802.3 standard. separate channels are provided for transmitting data from the mac to the lxt972m transceiver (txd), and for passing data received from the line (rxd) to the mac. each channel has its own clock, data bus, and control signals. the following signals are used to pass received data to the mac: ? col ? crs ? rx_clk ? rx_dv ? rx_er ? rxd[3:0] the following signals are used to transmit data from the mac: ? tx_clk ? tx_en ? txd[3:0] the lxt972m transceiver supplies both clock signals as well as separate outputs for carrier sense and collision. data transmission across the mii is normally implemented in 4-bit-wide nibbles. intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 37 document number: 302875-005 revision date: 27-oct-2005 5.6.1 mii clocks the lxt972m transceiver is the master clock source for data transmission, and it supplies both mii clocks (rx_clk and tx_clk). it automatically sets the clock speeds to match link conditions. ? when the link is operating at 100 mbps, the clocks are set to 25 mhz. ? when the link is operating at 10 mbps, the clocks are set to 2.5 mhz. figure 7 through figure 9 show the clock cycles for each mode. note: the transmit data and control signals must always be synchronized to tx_clk by the mac. the lxt972m transceiver samples these signals on the rising edge of tx_clk. figure 7. clocking for 10base-t figure 8. clocking for 100base-x r x_clk 2.5 mhz during auto-negotiation and 10base-t data & idle t x_clk 2.5 mhz during auto-negotiation and 10base-t data & idle constant 25 mhz x i b3390-01 r x_clk 2.5 mhz during auto-negotiation t x_clk constant 25 mhz x i 25 mhz once 100base-x link established 2.5 mhz during auto-negotiation 25 mhz once 100base-x link established b3391-01 intel ? lxt972m single-port 10/100 mbps phy transceiver 38 datasheet document number: 302875-005 revision date: 27-oct-2005 5.6.2 transmit enable the mac must assert tx_en the same time as the first nibble of preamble and de-assert tx_en after the last nibble of the packet. 5.6.3 receive data valid the lxt972m transceiver asserts rx_dv when it receives a valid packet. timing changes depend on line operating speed: ? for 100base-tx links, rx_dv is asserted from the first nibble of preamble to the last nibble of the data packet. ? for 10base-t links, the entire preamble is truncated. rx_dv is asserted with the first nibble of the start of frame delimiter (sfd) ?5d? and remains asserted until the end of the packet. figure 9. clocking for link down clock transition any clock 2.5 mhz clock clock transition time does not exceed 2x the nominal clock period: 10 mbps = 2.5 mhz 100 mbps = 25 mhz link-down condition/auto-negotiate enabled rx_clk tx_clk b3503-01 intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 39 document number: 302875-005 revision date: 27-oct-2005 5.6.4 carrier sense carrier sense (crs) is an asynchronous output. ? crs is always generated when the lxt972m transceiver receives a packet from the line. ? crs is also generated when the lxt972m transceiver is in half-duplex mode when a packet is transmitted. table 14 summarizes the conditions for assertion of carrier sense, data loopback, and collision signals. carrier sense is not generated when a packet is transmitted and in full-duplex mode. 5.6.5 error signals when the lxt972m transceiver is in 100 mbps mode and receives an invalid symbol from the network, it asserts rx_er and drives ?0101? on the rxd pins. the tx_er function that forces ?h? symbols out on the tpop/tpon twisted pair is not implemented in the lxt972m transceiver. 5.6.6 collision the lxt972m transceiver asserts its collision signal asynchronously to any clock whenever the line state is half-duplex and the transmitter and receiver are active at the same time. table 14 summarizes the conditions for assertion of carrier sense, data loopback, and collision signals. table 14. carrier sense, loopback, and collision conditions speed duplex condition carrier sense test loop- back 1, 2 operational loop- back 1, 2 collision 100 mbps full-duplex receive only yes no none half-duplex transmit or receive no no transmit and receive 10 mbps full-duplex receive only yes no none half-duplex, register bit 16.8 = 0 transmit or receive yes yes transmit and receive half-duplex, register bit 16.8 = 1 transmit or receive no no transmit and receive 1. test loopback is enabled when register bit 0.14 = 1. 2. for descriptions of test loopback and operational loopback, see section 5.6.7, ?loopback? on page 40 . intel ? lxt972m single-port 10/100 mbps phy transceiver 40 datasheet document number: 302875-005 revision date: 27-oct-2005 5.6.7 loopback the lxt972m transceiver provides the following loopback functions: ? section 5.6.7.1, ?operational loopback? ? section 5.6.7.2, ?internal digital loopback (test loopback)? figure 10 shows lxt972m transceiver loopback paths. 5.6.7.1 operational loopback ? operational loopback is provided for 10 mbps half-duplex links when register bit 16.8 = 0. data that the mac (txdata) transmits loops back on the receive side of the mii (rxdata). ? operational loopback is not provided for 100 mbps links, full-duplex links, or when register 16.8 = 1. figure 10. intel ? lxt972m transceiver loopback paths b3485-01 10t loopback digital block mii 100x loopback analog block intel? lxt972m transceiver operational loopback test loopback tx driver intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 41 document number: 302875-005 revision date: 27-oct-2005 5.6.7.2 internal digital loopback (test loopback) a test loopback function is provided for diagnostic testing of the lxt972m transceiver. during test loopback, twisted-pair and fiber interfaces are disabled. data transmitted by the mac is internally looped back by the lxt972m transceiver and returned to the mac. test loopback is available for both 100base-tx and 10base-t operation, and is enabled by setting the following register bits: ? register bit 0.14 = 1 (setting to enable loopback mode) ? register bit 0.8 = 1 (setting for full-duplex mode) ? register bit 0.12 = 0. (disable auto-negotiation.) 5.7 100 mbps operation 5.7.1 100base-x network operations during 100base-x operation, the lxt972m transceiver transmits and receives 5-bit symbols across the network link. figure 11 shows the structure of a standard frame packet in 100base-x mode. when the mac is not actively transmitting data, the lxt972m transceiver sends out idle symbols on the line. as figure 11 shows, the mac starts each transmission with a preamble pattern. as soon as the lxt972m transceiver detects the start of preamble, it transmits a start-of-stream delimiter (ssd, symbols j and k) to the network. it then encodes and transmits the rest of the packet, including the balance of the preamble, the sfd, packet data, and crc. once the packet ends, the lxt972m transceiver transmits the end-of-stream delimiter (esd, symbols t and r) and then returns to transmitting idle symbols. for details on the symbols used, see 4b/5b coding listed in table 15, ?4b/5b coding? on page 46 . figure 11. 100base-x frame format p0 p1 p6 sfd 64-bit preamble (8 octets) start-of-frame delimiter (sfd) da da sa sa destination and source address (6 octets each) l1 l2 packet length (2 octets) d0 d1 dn data field (pad to minimum packet size) frame check field (4 octets) crc i0 interframe gap / idle code (> 12 octets) replaced by /t/r/ code-groups end-of-stream delimiter (esd) ifg replaced by /j/k/ code-groups start-of-stream delimiter (ssd) b3466-01 intel ? lxt972m single-port 10/100 mbps phy transceiver 42 datasheet document number: 302875-005 revision date: 27-oct-2005 as shown in figure 12, in 100base-tx mode, the lxt972m transceiver scrambles and transmits the data to the network using mlt-3 line code. mlt-3 signals received from the network are de-scrambled, decoded, and sent across the mii to the mac. figure 12. 100base-tx data path s0 s1 s2 s3 s4 parallel to serial serial to parallel mlt3 0 +1 -1 00 transition = 1. no transition = 0. all transitions must follow pattern: 0, +1, 0, -1, 0, +1... scrambler bypass data flow s0 s1 s2 s3 s4 standard data flow d0 d1 d2 d3 parallel to serial serial to parallel d0 d1 d2 d3 4b/5b s0 s1 s2 s3 s4 mlt3 0 +1 -1 00 transition = 1. no transition = 0. all transitions must follow pattern: 0, +1, 0, -1, 0, +1... scramble de- scramble b3467-01 intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 43 document number: 302875-005 revision date: 27-oct-2005 figure 13 shows normal reception with no errors. as shown in figure 14 , when the lxt972m transceiver receives invalid symbols from the line, it asserts rx_er. figure 13. 100base-tx reception with no errors rx_clk rx_dv rxd<3:0> rx_er preamble sfd sfd da da da da crc crc crc crc b3468-01 figure 14. 100base-tx reception with invalid symbol rx_clk rx_dv rxd<3:0> rx_er preamble sfd sfd da da xx xx xx xx xx xx xx xx xx xx b3469-01 intel ? lxt972m single-port 10/100 mbps phy transceiver 44 datasheet document number: 302875-005 revision date: 27-oct-2005 5.7.2 collision indication figure 15 shows normal transmission. upon detection of a collision, the col output is asserted and remains asserted for the duration of the collision as shown in figure 16 . figure 15. 100base-tx transmission with no errors da da da da da da da da da tx_clk tx_en txd<3:0> crs col pr ea mb le b3470-01 figure 16. 100base-tx transmission with collision jam tx_clk tx_en txd<3:0> crs col pr ea mb l e jam jam jam b3471-01 intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 45 document number: 302875-005 revision date: 27-oct-2005 5.7.3 100base-x protocol sublayer operations with respect to the 7-layer communications model, the lxt972m transceiver is a physical layer 1 (phy) device. the lxt972m transceiver implements the following sublayers of the reference model defined by the ieee 802.3 standard, and discussed from the reference model point of view: ? section 5.7.3.1, ?physical coding sublayer? ? section 5.7.3.2, ?physical medium attachment sublayer? ? section 5.7.3.3, ?twisted-pair physical medium dependent sublayer? figure 17 shows the lxt972m transceiver protocol sublayers. figure 17. intel ? lxt972m protocol sublayers encoder/decoder serializer/de-serializer link/carrier detect pcs sublayer pma sublayer mii interface intel? lxt972m transceiver 100base-tx scrambler/ de-scrambler pmd sublayer b3514-01 intel ? lxt972m single-port 10/100 mbps phy transceiver 46 datasheet document number: 302875-005 revision date: 27-oct-2005 5.7.3.1 physical coding sublayer the physical coding sublayer (pcs) provides the mii interface, as well as the 4b/5b encoding/ decoding function. for 100base-tx operation, the pcs layer provides idle symbols to the pmd-layer line driver as long as tx_en is de-asserted. 5.7.3.1.1 preamble handling when the mac asserts tx_en, the pcs substitutes a /j/k symbol pair, also known as the start-of- stream delimiter (ssd), for the first two nibbles received across the mii. the pcs layer continues to encode the remaining mii data, following the 4b/5b coding in table 15 , until tx_en is de- asserted. it then returns to supplying idle symbols to the line driver. in the receive direction, the pcs layer performs the opposite function, substituting two preamble nibbles for the ssd. in 100 mbps operation, preamble is always passed through the pcs layer to the mii interface. table 15. 4b/5b coding (sheet 1 of 2) code type 4b code 3 2 1 0 name 5b code 4 3 2 1 0 interpretation data 0 0 0 0 0 1 1 1 1 0 data 0 0 0 0 1 1 0 1 0 0 1 data 1 0 0 1 0 2 1 0 1 0 0 data 2 0 0 1 1 3 1 0 1 0 1 data 3 0 1 0 0 4 0 1 0 1 0 data 4 0 1 0 1 5 0 1 0 1 1 data 5 0 1 1 0 6 0 1 1 1 0 data 6 0 1 1 1 7 0 1 1 1 1 data 7 1 0 0 0 8 1 0 0 1 0 data 8 1 0 0 1 9 1 0 0 1 1 data 9 1 0 1 0 a 1 0 1 1 0 data a 1 0 1 1 b 1 0 1 1 1 data b 1 1 0 0 c 1 1 0 1 0 data c 1 1 0 1 d 1 1 0 1 1 data d 1 1 1 0 e 1 1 1 0 0 data e 1 1 1 1 f 1 1 1 0 1 data f idle undefined i 1 1 1 1 11 used as inter-stream fill code 1. the /i/ (idle) code group is sent continuously between frames. 2. the /j/ and /k/ (ssd) code groups are always sent in pairs, and /k/ follows /j/. 3. the /t/ and /r/ (esd) code groups are always sent in pairs, and /r/ follows /t/. 4. an /h/ (error) code group is used to signal an error condition. intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 47 document number: 302875-005 revision date: 27-oct-2005 control 0 1 0 1 j 2 1 1 0 0 0 start-of-stream delimiter (ssd), part 1 of 2 0 1 0 1 k 2 1 0 0 0 1 start-of-stream delimiter (ssd), part 2 of 2 undefined t 3 0 1 1 0 1 end-of-stream delimiter (esd), part 1 of 2 undefined r 3 0 0 1 1 1 end-of-stream delimiter (esd), part 2 of 2 invalid undefined h 4 0 0 1 0 0 transmit error. used to force signaling errors undefined invalid 0 0 0 0 0 invalid undefined invalid 0 0 0 0 1 invalid undefined invalid 0 0 0 1 0 invalid undefined invalid 0 0 0 1 1 invalid undefined invalid 0 0 1 0 1 invalid undefined invalid 0 0 1 1 0 invalid undefined invalid 0 1 0 0 0 invalid undefined invalid 0 1 1 0 0 invalid undefined invalid 1 0 0 0 0 invalid undefined invalid 1 1 0 0 1 invalid table 15. 4b/5b coding (sheet 2 of 2) code type 4b code 3 2 1 0 name 5b code 4 3 2 1 0 interpretation 1. the /i/ (idle) code group is sent continuously between frames. 2. the /j/ and /k/ (ssd) code groups are always sent in pairs, and /k/ follows /j/. 3. the /t/ and /r/ (esd) code groups are always sent in pairs, and /r/ follows /t/. 4. an /h/ (error) code group is used to signal an error condition. intel ? lxt972m single-port 10/100 mbps phy transceiver 48 datasheet document number: 302875-005 revision date: 27-oct-2005 5.7.3.2 physical medium attachment sublayer 5.7.3.2.1 link in 100 mbps mode, link is established when the descrambler becomes locked and remains locked for approximately 50 ms. link remains up unless the descrambler receives less than 16 consecutive idle symbols in any 2 ms period. this operation filters out small noise hits that may disrupt the link. in 100 mbps mode, link is established when the descrambler becomes locked and remains locked for approximately 50 ms. link remains up unless the descrambler receives less than 16 consecutive idle symbols in any 2 ms period. this operation filters out small noise hits that may disrupt the link. for short periods, mlt-3 idle waveforms meet all criteria for 10base-t start delimiters. a working 10base-t receive may temporarily indicate link to 100base-tx waveforms. however, the phy does not bring up a permanent 10 mbps link. the lxt972m transceiver reports link failure through the mii status bits (register bits 1.2 and 17.10). link failure causes the lxt972m transceiver to re-negotiate if auto-negotiation is enabled. 5.7.3.2.2 link failure override the lxt972m transceiver normally transmits data packets only if it detects the link is up. setting register bit 16.14 = 1 overrides this function, allowing the lxt972m transceiver to transmit data packets even when the link is down. this feature is provided as a transmit diagnostic tool. note: auto-negotiation must be disabled to transmit data packets in the absence of link. if auto- negotiation is enabled, the lxt972m transceiver automatically transmits flp bursts if the link is down. caution: during normal operation, intel does not recommend setting register bit 16.14 for 100 mbps receive functions because receive errors may be generated. 5.7.3.2.3 carrier sense for 100base-tx links, a start-of-stream delimiter ( ssd) or /j/k symbol pair causes assertion of carrier sense (crs). an end-of-stream delimiter (esd) or /t/r symbol pair causes de-assertion of crs. the pma layer also de-asserts crs if idle symbols are received without /t/r. however, in this case rx_er is asserted for one clock cycle when crs is de-asserted. intel does not recommend using crs for interframe gap (ifg) timing for the following reasons: ? crs de-assertion time is slightly longer than crs assertion time. as a result, an ifg interval appears somewhat shorter to the mac than it actually is on the wire. ? crs de-assertion is not aligned with tx_en de-assertion on transmit loopbacks in half- duplex mode. 5.7.3.2.4 receive data valid the lxt972m transceiver asserts rx_dv to indicate that the received data maps to valid symbols. in 100 mbps operation, rx_dv is active with the first nibble of preamble. intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 49 document number: 302875-005 revision date: 27-oct-2005 5.7.3.3 twisted-pair physical medium dependent sublayer the twisted-pair physical medium dependent (pmd) layer provides signal scrambling and de- scrambling functions, line coding and decoding functions (mlt-3 for 100base-tx, manchester for 10base-t), as well as receiving, polarity correction, and baseline wander correction functions. 5.7.3.3.1 scrambler/descrambler the purpose of the scrambler/descrambler is to spread the signal power spectrum and further reduce emi using an 11-bit, data-independent polynomial. the receiver automatically decodes the polynomial whenever idle symbols are received. scrambler seeding. once the transmit data (or idle symbols) are properly encoded, they are scrambled to further reduce emi and to spread the power spectrum using an 11-bit scrambler seed. five seed bits are determined by the phy address, and the remaining bits are hard coded in the design. scrambler bypass. the scrambler/de-scrambler can be bypassed by setting register bit 16.12 = 1. scrambler bypass is provided for diagnostic and test support. 5.7.3.3.2 polarity correction the 100 mbps twisted pair signaling is not polarity sensitive. as a result, the polarity status is not a valid status indicator. 5.7.3.3.3 baseline wander correction the lxt972m transceiver provides a baseline wander correction function for when the lxt972m transceiver is under network operating conditions. the mlt3 coding scheme used in 100base-tx is by definition ?unbalanced?. as a result, the average value of the signal voltage can ?wander? significantly over short time intervals (tenths of seconds). this wander can cause receiver errors at long-line lengths (100 meters) in less robust designs. exact characteristics of the wander are completely data dependent. the lxt972m transceiver baseline wander correction characteristics allow the device to recover error-free data while receiving worst-case packets over all cable lengths. 5.7.3.3.4 programmable slew rate control the lxt972m transceiver device supports a programmable slew-rate mechanism whereby one of four pre-selected slew rates can be used. (for details, see table 56, ?transmit control register - address 30, hex 1e? on page 89 .) the slew-rate mechanism allows the designer to optimize the output waveform to match the characteristics of the magnetics. intel ? lxt972m single-port 10/100 mbps phy transceiver 50 datasheet document number: 302875-005 revision date: 27-oct-2005 5.8 10 mbps operation the lxt972m transceiver operates as a standard 10base-t transceiver and supports standard 10 mbps functions. during 10base-t operation, the lxt972m transceiver transmits and receives manchester-encoded data across the network link. when the mac is not actively transmitting data, the lxt972m transceiver drives link pulses onto the line. in 10base-t mode, the polynomial scrambler/de-scrambler is inactive. manchester-encoded signals received from the network are decoded by the lxt972m transceiver and sent across the mii to the mac. note: 5.8.1 10base-t preamble handling the lxt972m transceiver offers two options for preamble handling, selected by register bit 16.5. ? in 10base-t mode when register bit 16.5 = 0, the lxt972m transceiver strips the entire preamble off of received packets. crs is asserted coincident with the start of the preamble. rx_dv is held low for the duration of the preamble. when rx_dv is asserted, the very first two nibbles driven by the lxt972m transceiver are the sfd ?5d? hex followed by the body of the packet. ? in 10base-t mode when register bit 16.5 = 1, the lxt972m transceiver passes the preamble through the mii and asserts rx_dv and crs simultaneously. (in 10base-t loopback, the lxt972m transceiver loops back whatever the mac transmits to it, including the preamble.) 5.8.2 10base-t carrier sense for 10base-t links, crs assertion is based on reception of valid preamble, and crs de-assertion is based on reception of an end-of-frame (eof) marker. register bit 16.7 allows crs de-assertion to be synchronized with rx_dv de-assertion. for details, see table 51, ?configuration register - address 16, hex 10? on page 84 . 5.8.3 10base-t dribble bits the lxt972m transceiver handles dribble bits in all modes. if one to four dribble bits are received, the nibble is passed across the mii, padded with ones if necessary. if five to seven dribble bits are received, the second nibble is not sent to the mii bus. intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 51 document number: 302875-005 revision date: 27-oct-2005 5.8.4 10base-t link integrity test in 10base-t mode, the lxt972m transceiver always transmits link pulses. ? if the link integrity test function is enabled (the normal configuration), the lxt972m transceiver monitors the connection for link pulses. once link pulses are detected, data transmission is enabled and remains enabled as long as either the link pulses or data transmission continue. if the link pulses stop, the data transmission is disabled. ? if the link integrity test function is disabled (which can be done by setting configuration register bit 16.14 to ?1?), the lxt972m transceiver transmits to the connection regardless of detected link pulses. 5.8.5 link failure link failure occurs if the link integrity test is enabled and link pulses or packets stop being received. if this condition occurs, the lxt972m transceiver returns to the auto-negotiation phase if auto-negotiation is enabled. if the link integrity test function is disabled by setting configuration register bit 16.14 to ?1?, the lxt972m transceiver transmits packets, regardless of link status. 5.8.6 10base-t sqe (heartbeat) by default, the signal quality error (sqe) or heartbeat function is disabled on the lxt972m transceiver. to enable this function, set register bit 16.9 = 1. when this function is enabled, the lxt972m transceiver asserts its col output for 5 to 15 bit times (bt) after each packet. 5.8.7 10base-t jabber if a transmission exceeds the jabber timer, the lxt972m transceiver disables the transmit and loopback functions. for jabber timing parameters, see figure 26, ?intel? lxt972m transceiver 10base-t jabber and unjabber timing? on page 69 . the lxt972m transceiver automatically exits jabber mode after the unjabber time has expired. this function can be disabled by setting register bit 16.10 = 1. 5.8.8 10base-t polarity correction the lxt972m transceiver automatically detects and corrects for the condition in which the receive signal (tpip/n) is inverted. reversed polarity is detected if eight inverted link pulses - or four inverted end-of-frame (eof) markers - are received consecutively. if link pulses or data are not received by the maximum receive time-out period (96 to 128 ms), the polarity state is reset to a non-inverted state. when polarity reversal is detected in 10base-t operation, register 17.5 is set to 1. (for details, see bit 17.5 in table 52, ?status register #2 - address 17, hex 11? on page 85 .) intel ? lxt972m single-port 10/100 mbps phy transceiver 52 datasheet document number: 302875-005 revision date: 27-oct-2005 5.9 monitoring operations 5.9.1 monitoring auto-negotiation auto-negotiation can be monitored as follows: ? register bit 17.7 is set to ?1? once the auto-negotiation process is completed. ? register bits 1.2 and 17.10 are set to ?1? once the link is established. ? register bits 17.14 and 17.9 can be used to determine the link operating conditions (speed and duplex). note: when the lxt972m transceiver detects incorrect polarity for a 10base-t operation, register bit 17.5 is set to ?1?. 5.9.2 monitoring next page exchange the lxt972m transceiver offers an alternate next page mode to simplify the next page exchange process. normally, register bit 6.1 (page received) remains set until read. when alternate next page mode is enabled, register bit 6.1 is automatically cleared whenever a new negotiation process takes place. this action prevents the user from reading an old value in bit 6.1 and assuming that registers 5 and 8 (partner ability) contain valid information. additionally, the lxt972m transceiver uses register bit 6.5 to indicate when the current received page is the base page. this information is useful for recognizing when next pages must be resent due to a new negotiation process starting. register bits 6.1 and 6.5 are cleared when read. intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 53 document number: 302875-005 revision date: 27-oct-2005 5.9.3 led functions the lxt972m transceiver has these direct led driver pins: led/cfg1, led/cfg2, and led/ cfg3. on power-up, all the drivers are asserted for approximately 1 second after reset de-asserts. each led driver can be programmed using the led configuration register ( table 54, ?led configuration register - address 20, hex 14? on page 87 ) to indicate one of the following conditions: ? collision condition ? duplex mode ? link status ? operating speed ? receive activity ? transmit activity the led drivers can also be programmed to display various combined status conditions. for example, setting register bits 20.15:12 to ?1101? produces the following combination of link and activity indications: ? if link is down, led is off. if activity is detected from the mac, the led still blinks even if the link is down. ? if link is up, led is on. ? if link is up and activity is detected, the led blinks at the stretch interval selected by register bits 20.3:2 and continues to blink as long as activity is present. for the lxt972m transceiver, the led driver pins also provide initial configuration settings. the led pins are sensitive to polarity and automatically pull up or pull down to configure for either open drain or open collector circuits (10 ma max current rating) as required by the hardware configuration. for details, see the discussion of ?hardware configuration settings? on page 33 . intel ? lxt972m single-port 10/100 mbps phy transceiver 54 datasheet document number: 302875-005 revision date: 27-oct-2005 5.9.4 led pulse stretching the led configuration register also provides optional led pulse stretching to 30, 60, or 100 ms. the pulse stretch time is extended further if the event occurs again during this pulse stretch period. when an event such as receiving a packet occurs, the event is edge detected and it starts the stretch timer. the led driver remains asserted until the stretch timer expires. if another event occurs before the stretch timer expires, then the stretch timer is reset and the stretch time is extended. when a long event (such as duplex status) occurs, the event is edge detected and it starts the stretch timer. when the stretch timer expires, the edge detector is reset so that a long event causes another pulse to be generated from the edge detector, which resets the stretch timer and causes the led driver to remain asserted. figure 18 shows how the stretch operation functions. figure 18. led pulse stretching event led note: the direct drive led outputs in this diagram are shown as active low. stretch stretch stretch b3475-01 intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 55 document number: 302875-005 revision date: 27-oct-2005 5.10 boundary scan (jtag 1149.1) functions the lxt972m transceiver includes a ieee 1149.1 boundary scan test port for board level testing. all digital input, output, and input/output pins are accessible. note: for the related bsdl file, contact your local sales office or access the intel website (www.intel.com) . 5.10.1 boundary scan interface the boundary scan interface consists of five pins (tms, tdi, tdo, trst_l, and tck). it includes a state machine, data register array, and instruction register. the tms and tdi pins are pulled up internally. tck is pulled down internally. tdo does not have an internal pull-up or pull- down. 5.10.2 state machine the tap controller is a state machine, with 16 states driven by the tck and tms pins. upon reset, the test_logic_reset state is entered. the state machine is also reset when tms and tdi are high for five tck periods. 5.10.3 instruction register after the state machine resets, the idcode instruction is always invoked. the decode logic ensures the correct data flow to the data registers according to the current instruction. table 16 lists valid jtag instructions for the lxt972m transceiver. table 16. valid jtag instructions name code description mode data register extest 1111 1111 1110 1000 external test test bsr idcode 1111 1111 1111 1110 id code inspection normal id reg sample 1111 1111 1111 1000 sample boundary normal bsr highz 1111 1111 1100 1111 force float normal bypass clamp 1111 1111 1110 1111 contr ol boundary to 1/0 test bypass bypass 1111 1111 1111 1111 bypass scan normal bypass intel ? lxt972m single-port 10/100 mbps phy transceiver 56 datasheet document number: 302875-005 revision date: 27-oct-2005 5.10.4 boundary scan register each boundary scan register (bsr) cell has two stages. a flip-flop and a latch are used for the serial shift stage and the parallel output stage. table 17 lists the four bsr modes of operation. 5.10.5 device id register table 18 lists the bits for the device id register. for the current version of the jedec continuation characters, see the specification update for the lxt972m transceiver. table 17. bsr mode of operation mode description 1capture 2shift 3 update 4 system function table 18. device id register for intel ? lxt972m transceiver bits 31:28 bits 27:12 bits 11:8 bits 7:1 bit 0 version part id (hex) jedec continuation characters jedec id 1 reserved xxxx 03cb 0000 111 1110 1 1. the jedec id is an 8-bit identifier. the msb is for parity and is ignored. the intel jedec id is fe (1111 1110) , which becomes 111 1110. intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 57 document number: 302875-005 revision date: 27-oct-2005 6.0 application information 6.1 magnetics information the lxt972m transceiver requires a 1:1 ratio for both the receive and transmit transformers. the transformer isolation voltage should be rated at 2 kv to protect the circuitry from static voltages across the connectors and cables. for transformer/magnetics requirements, see table 19 . note: before committing to a specific component, contact the manufacturer for current product specifications and validate the magnetics for the specific application. 6.2 typical twisted-pair interface table 20 provides a comparison of the rj-45 connections for nic and switch applications in a typical twisted-pair interface setting. table 19. magnetics requirements parameter min nom max units test condition rx turns ratio ? 1 : 1 ? ? ? tx turns ratio ? 1 : 1 ? ? ? insertion loss 0.0 0.6 1.1 db ? primary inductance 350 ? ? h? transformer isolation ? 1.5 ? kv ? differential to common mode rejection 40 ? ? db 0.1 to 60 mhz 35 ? ? db 60 to 100 mhz return loss -16 ? ? db 30 mhz -10 ? ? db 80 mhz table 20. i/o pin comparison of nic and switch rj-45 setups symbol rj-45 switch nic tpip 1 3 tpin 2 6 tpop 3 1 tpon 6 2 intel ? lxt972m single-port 10/100 mbps phy transceiver 58 datasheet document number: 302875-005 revision date: 27-oct-2005 figure 19 shows the lxt972m transceiver in a typical twisted-pair interface, with the rj-45 connections crossed over for a switch configuration. figure 19. intel ? lxt972m transceiver typical twisted-pair interface - switch 1. center tap current may be supplied from 3.3 v vcca as shown. additional power savings may be realized by supplying the center tap from a 2.5 v current source. a separate ferrite bead (rated at 50 ma) should be used to supply center tap current. 2. the 100 transmit load termination resistor typically required is integrated in the lxt972m transceiver. 3. magnetics without a receive pair center-tap do not require a 2 kv termination. 4. rj-45 connections shown are for a standard switch application. for a standard nic rj-45 setup, see figure 20 on page 59 . tpip tpin rj-45 * = 0.001 f / 2.0 kv to twisted-pair network 3 6 1 2 1:1 intel? lxt972m transceiver 50 50 50 50 50 50 4 5 8 7 1:1 1 tpop tpon vcca gnd 0.1 f .01 f 2 270 pf 5% 270 pf 5% 0.01 f 50 1% 50 1% ** 3 4 0.1 f b3515-02 intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 59 document number: 302875-005 revision date: 27-oct-2005 figure 20 shows the lxt972m transceiver in a typical twisted-pair interface, with the rj-45 connections configured for a nic application. figure 20. intel ? lxt972m transceiver typical twisted-pair interface - nic 1. center tap current may be supplied from 3.3 v vcca as shown. additional power savings may be realized by supplying the center tap from a 2.5 v current source. a separate ferrite bead (rated at 50 ma) should be used to supply center-tap current. 2. the 100 transmit load termination resistor typically required is integrated in the lxt972m transceiver. 3. magnetics without a receive pair center tap do not require a 2 kv termination. 4. rj-45 connections shown for standard nic. tx/rx crossover may be required for repeater and switch applications. tpip tpin * = 0.001 f / 2.0 kv to twisted-pair network 1:1 intel? lxt972m transceiver 1:1 1 tpop tpon vcca gnd 0.1 f .01 f 2 270 pf 5% 270 pf 5% 0.01 f 50 1% 50 1% ** 3 sd/tp_l 6 3 8 7 5 4 1 2 50 50 50 rj-45 50 50 50 4 0.1 f b3513-01 intel ? lxt972m single-port 10/100 mbps phy transceiver 60 datasheet document number: 302875-005 revision date: 27-oct-2005 figure 21 shows a typical media independent interface (mii) for the lxt972m transceiver. figure 21. intel ? lxt972m transceiver typical media independent interface mac tx_en txd[3:0] tx_clk rx_dv rx_er rxd[3:0] crs col rx_clk intel? lxt972m transceiver trans- former rj-45 b3480-02 intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 61 document number: 302875-005 revision date: 27-oct-2005 7.0 electrical specifications this chapter includes test specifications for the lxt972m transceiver. these specifications are guaranteed by test except where noted ?by design?. ? table 21 lists the absolute maximum ratings. ? table 22 lists the recommended operating conditions. ? table 23 through table 39 list the minimum and maximum values that apply over the recommended operating conditions specified. 7.1 electrical parameters table 21 lists absolute maximum ratings for the lxt972m transceiver. caution: ? exceeding the absolute maximum rating values may cause permanent damage. ? functional operation under these conditions is not implied. ? exposure to maximum rating conditions for extended periods may affect device reliability. table 22 lists the recommended operating conditions for the lxt972m transceiver. table 21. absolute maximum ratings for intel ? lxt972m transceiver parameter sym min max units supply voltage v cc -0.3 4.0 v storage temperature t st -65 +150 oc table 22. recommended operating conditions for intel ? lxt972m transceiver parameter sym min typ 1 max units recommended operating temperature t opa 0?70oc recommended supply voltage 2 - analog and digital vcca, vccd 3.14 3.3 3.45 v recommended supply voltage 2 - i/o vccio 2.35 ? 3.45 v vcc current - 100 base-tx i cc ?92110ma vcc current - 10 base-t i cc ?6682ma hard power down i cc ?? 1ma soft power down icc ? 51 ? ma auto-negotiation i cc ?90110ma 1. typical values are at 25 c and are for design aid only, not guaranteed, and not subject to production testing. 2. voltages are with respect to ground unless otherwise specified. intel ? lxt972m single-port 10/100 mbps phy transceiver 62 datasheet document number: 302875-005 revision date: 27-oct-2005 table 23 lists digital i/o characteristics for all pins except the mii, xi/xo, and led/cfg pins. table 24 lists digital i/o characteristics for the mii pins. table 23. digital i/o characteristics (except for mii, xi/xo, and led/cfg pins) parameter sym min typ 2 max units test conditions input low voltage v il ??0.8v? input high voltage v ih 2.0 ? ? v ? input current i i -10 ? 10 a 0.0 < v i < v cc output low voltage v ol ??0.4vi ol = 4 ma output high voltage v oh 2.4 ? ? v i oh = -4 ma 1. typical values are at 25 c and are for design aid only, not guaranteed, and not subject to production testing. table 24. digital i/o characteristics 1 - mii pins parameter sym min typ 2 max units test conditions input low voltage v il ??0.8v? input high voltage v ih 2.0 ? ? v ? input current i i -10 ? 10 a0.0 < v i < vccio output low voltage v ol ??0.4vi ol = 4 ma output high voltage v oh 2.2 ? ? v i oh = -4 ma, vccio = 3.3 v v oh 2.0 ? ? v i oh = -4 ma, vccio = 2.5 v driver output resistance (line driver output enabled) r o 3 ? 100 ? vccio = 2.5 v r o 3 ? 100 ? vccio = 3.3 v 1. mii digital i/o pins are tolerant to 5 v inputs. 2. typical values are at 25 c and are for design aid only, not guaranteed, and not subject to production testing. 3. parameter is guaranteed by design and not subject to production testing. intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 63 document number: 302875-005 revision date: 27-oct-2005 table 25 lists the i/o characteristics for the refclk/xi and xo pins. table 26 lists the i/o characteristics for the lxt972m transceiver led/cfg pins. table 25. i/o characteristics - refclk/xi and xo pins parameter symbol min typ 1 max units test conditions input low voltage v il ??0.8v ? input high voltage v ih 2.0 ? ? v ? input clock frequency tolerance 2 f?? 100 ppm ? input clock duty cycle 2 tdc 35 ? 65 % ? input capacitance c in ?3.0?pf ? 1. typical values are at 25 c and are for design aid only, not guaranteed, and not subject to production testing. 2. parameter is guaranteed by design and not subject to production testing. table 26. i/o characteristics - led/cfg pins parameter symbol min typ max units test conditions input low voltage v il ??0.8 v ? input high voltage v ih 2.0 ? ? v ? input current i i -10 ? 10 a0 < v i < vccio output low voltage v ol ??0.4 vi ol = 10 ma output high voltage v oh 2.0 ? ? v i oh = -10 ma intel ? lxt972m single-port 10/100 mbps phy transceiver 64 datasheet document number: 302875-005 revision date: 27-oct-2005 table 27 lists the 100base-tx characteristics. table 28 lists the 10base-t characteristics. table 29 lists the 10base-t link integrity timing characteristics. table 27. 100base-tx transceiver characteristics parameter symbol min typ 1 max units test conditions peak differential output voltage v p 0.95 ? 1.05 v note 2 signal amplitude symmetry vss 98 ? 102 % note 2 signal rise/fall time t rf 3.0 ? 5.0 ns note 2 rise/fall time symmetry t rfs ? ? 0.5 ns note 2 duty cycle distortion d cd 35 50 65 % offset from 16 ns pulse width at 50% of pulse peak overshoot/undershoot v os ?? 5 % ? jitter (measured differentially) ? ? ? 1.4 ns ? 1. typical values are at 25 c and are for design aid only, not guaranteed, and not subject to production testing. 2. measured at the line side of the transformer, line replaced by 100 (+/-1%) resistor. table 28. 10base-t transceiver characteristics parameter symbol min typ max units test conditions transmitter peak differential output voltage v op 2.2 2.5 2.8 v with transformer, line replaced by 100 resistor transition timing jitter added by the mau and pls sections ?0211ns after line model specified by ieee 802.3 for 10base-t mau receiver receive input impedance z in ??22k ? differential squelch threshold v ds 300 420 585 mv ? table 29. 10base-t link integrity timing characteristics parameter symbol min typ max units test conditions time link loss receive t ll 50 ? 150 ms ? link pulse t lp 2 ? 7 link pulses ? link min receive timer t lr m in 2?7 ms ? link max receive timer t lr m ax 50 ? 150 ms ? link transmit period tlt 8 ? 24 ms ? link pulse width tlpw 60 ? 150 ns ? 1. typical values are at 25 c and are for design aid only, not guaranteed, and not subject to production testing. intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 65 document number: 302875-005 revision date: 27-oct-2005 7.2 timing diagrams figure 22. intel ? lxt972m transceiver 100base-tx receive timing ta ble 3 0. intel ? lxt972m transceiver 100base-tx receive timing parameters parameter sym min typ 1 max units 2 test conditions rxd[3:0], rx_dv, rx_er 3 setup to rx_clk high t1 10 ? ? ns ? rxd[3:0], rx_dv, rx_er hold from rx_clk high t2 10 ? ? ns ? crs asserted to rxd[3:0], rx_dv t3 3 ? 5 bt ? receive start of ?j? to crs asserted t4 12 ? 16 bt ? receive start of ?t? to crs de-asserted t5 10 ? 17 bt ? receive start of ?j? to col asserted t6 16 ? 22 bt ? receive start of ?t? to col de-asserted t7 17 ? 20 bt ? 1. typical values are at 25 c and are for design aid only, not guaranteed, and not subject to production testing. 2. bt (bit time) is the duration of one bit as transferred to and from the mac and is the reciprocal of the bit rate. 100base-t bit time = 10 -8 s or 10 ns. 3. rx_er is not shown in the figure. t4 t5 t3 t6 t7 0 ns 250 ns crs rx_dv rxd[3:0] rx_clk col t1 t2 tpi b3492-03 note: timing diagram depicts 4b mode. intel ? lxt972m single-port 10/100 mbps phy transceiver 66 datasheet document number: 302875-005 revision date: 27-oct-2005 figure 23 does not show the tx_er signal. . figure 23. intel ? lxt972m transceiver 100base-tx transmit timing t1 t2 t5 t3 t4 0ns 250ns txclk tx_en txd[3:0] tpo crs b3454-03 note: timing diagram depicts 4b mode. table 31. intel ? lxt972m transceiver 100base-tx transmit timing parameters parameter symbol min typ 1 max units 2 test conditions txd[3:0], tx_en setup to tx_clk high t1 12 ? ? ns ? txd[3:0], tx_en hold from tx_clk high t2 0 ? ? ns ? tx_en sampled to crs asserted t3 20 ? 24 bt ? tx_en sampled to crs de-asserted t4 24 ? 28 bt ? tx_en sampled to tpo out (tx latency) t5 5.3 ? 5.7 bt ? 1. typical values are at 25 c and are for design aid only, not guaranteed, and not subject to production testing. 2. bt (bit time) is the duration of one bit as transferred to and from the mac and is the reciprocal of the bit rate. 100base-t bit time = 10 -8 s or 10 ns. intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 67 document number: 302875-005 revision date: 27-oct-2005 figure 24. intel ? lxt972m transceiver 10base-t receive timing ta ble 3 2. intel ? lxt972m transceiver 10base-t receive timing parameter sym min typ 1 max units 2 test conditions rxd, rx_dv. setup to rx_clk high. t1 10 ? ? ns ? rxd, rx_dv, rx_er hold from rx_clk high t2 10 ? ? ns ? tpip/n in to rxd out (rx latency) t3 4.2 ? 6.6 bt ? crs asserted to rxd, rx_dv, rx_er asserted t4 5 ? 32 bt ? rxd, rx_dv, rx_er de-asserted to crs de-asserted t5 0.3 ? 0.5 bt ? tpi in to crs asserted t6 2 ? 28 bt ? tpi quiet to crs de-asserted t7 6 ? 10 bt ? tpi in to col asserted t8 1 ? 31 bt ? tpi quiet to col de-asserted t9 5 ? 10 bt ? 1. typical values are at 25 c and are for design aid only, not guaranteed, and not subject to production testing. 2. bt (bit time) is the duration of one bit as transferred to and from the mac and is the reciprocal of the bit rate. 10base-t bit time = 10 -7 s or 100 ns. rx_clk rxd, rx_dv, rx_er crs tpi t 3 t 4 t 2 t 6 t 1 t 7 t 5 col t 8 t 9 b3457-01 intel ? lxt972m single-port 10/100 mbps phy transceiver 68 datasheet document number: 302875-005 revision date: 27-oct-2005 figure 25. intel ? lxt972m transceiver 10base-t transmit timing table 33. intel ? lxt972m transceiver 10base-t transmit timing parameter symbol min typ 1 max units 2 test conditions txd, tx_en, setup to tx_clk high t1 10 ? ? ns ? txd, tx_en, hold from tx_clk high t2 0 ? ? ns ? tx_en sampled to crs asserted t3 ? 2 ? bt ? tx_en sampled to crs de-asserted t4 ? 1 ? bt ? tx_en sampled to tpo out (tx latency) t5 ? 72.5 ? bt ? 1. typical values are at 25 c and are for design aid only, not guaranteed, and not subject to production testing. 2. bt (bit time) is the duration of one bit as transferred to and from the mac and is the reciprocal of the bit rate. 10base-t bit time = 10 -7 s or 100 ns. tx_clk txd, tx_en crs tpo t 1 t 3 t 4 t 5 t 2 b3461-01 intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 69 document number: 302875-005 revision date: 27-oct-2005 figure 26. intel ? lxt972m transceiver 10base-t jabber and unjabber timing ta ble 3 4. intel ? lxt972m transceiver 10base-t jabber and unjabber timing parameter symbol min typ 1 max units test conditions maximum transmit time t1 20 ? 150 ms ? unjabber time t2 250 ? 750 ms ? 1. typical values are at 25 c and are for design aid only, not guaranteed, and not subject to production testing. txd col t 1 t 2 tx_en b3455-01 intel ? lxt972m single-port 10/100 mbps phy transceiver 70 datasheet document number: 302875-005 revision date: 27-oct-2005 figure 27. intel ? lxt972m transceiver 10base-t sqe (heartbeat) timing table 35. intel ? lxt972m transceiver 10base-t sqe (heartbeat) timing parameter symbol min typ 1 max units test conditions col (sqe) delay after tx_en off t1 0.65 ? 1.6 us ? col (sqe) pulse duration t2 0.5 ? 1.5 us ? 1. typical values are at 25 c and are for design aid only, not guaranteed, and not subject to production testing. tx_clk tx_en t 1 t 2 col b3458-01 intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 71 document number: 302875-005 revision date: 27-oct-2005 figure 28. intel ? lxt972m transceiver auto-negotiation and fast link pulse timing figure 29. intel ? lxt972m transceiver fast link pulse timing ta ble 3 6. intel ? lxt972m transceiver auto-negotiation / fast link pulse timing parameter symbol min typ 1 max units test conditions clock/data pulse width t1 ? 100 ? ns ? clock pulse to data pulse t2 55.5 ? 63.8 s? clock pulse to clock pulse t3 123 ? 127 s? flp burst width t4 ? 2 ? ms ? flp burst to flp burst t5 8 12 24 ms ? clock/data pulses per burst ? 17 ? 33 each clock pulse or data pulse ? 1. typical values are at 25 c and are for design aid only, not guaranteed, and not subject to production testing. tpop t1 t1 t2 t3 clock pulse data pulse clock pulse b3464-01 t4 t5 flp burst flp burst tpop b3465-01 intel ? lxt972m single-port 10/100 mbps phy transceiver 72 datasheet document number: 302875-005 revision date: 27-oct-2005 figure 30. intel ? lxt972m transceiver mdio input timing figure 31. intel ? lxt972m transceiver mdio output timing table 37. intel ? lxt972m transceiver mdio timing parameter symbol min typ 1 max units test conditions mdio setup before mdc, sourced by sta t1 10??ns ? mdio hold after mdc, sourced by sta t2 5 ??ns ? mdc to mdio output delay, sourced by phy t3 ? ? 150 ns ? mdc period t4 125 ? ? ns mdc = 8 mhz 1. typical values are at 25 c and are for design aid only, not guaranteed, and not subject to production testing. t1 mdc mdio t2 t3 mdc mdio t4 intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 73 document number: 302875-005 revision date: 27-oct-2005 figure 32. intel ? lxt972m transceiver power-up timing ta ble 3 8. intel ? lxt972m transceiver power-up timing parameter symbol min typ 1 max units test conditions voltage threshold v1 ? 2.9 ? v ? power up delay 2 t1 ? ? 300 s? 1. typical values are at 25 c and are for design aid only, not guaranteed, and not subject to production testing. 2. power-up delay is specified as a maximum value because it refers to the phy guaranteed performance. the phy comes out of reset after a delay of no more than 300 s. system designers should consider this value as a minimum value. after threshold v1 is reached, the mac should delay no less than 300 s before accessing the mdio port. t1 vcc mdio, and so on v1 b3494-01 intel ? lxt972m single-port 10/100 mbps phy transceiver 74 datasheet document number: 302875-005 revision date: 27-oct-2005 figure 33. intel ? lxt972m transceiver reset_l pulse width and recovery timing table 39. intel ? lxt972m transceiver reset_l pulse width and recovery timing parameter symbol min typ 1 max units test conditions reset_l pulse width t1 10 ? ? ns ? reset_l recovery delay 2 t2 ? 300 s? 1. typical values are at 25 c and are for design aid only, not guaranteed, and not subject to production testing. 2. reset recovery delay is specified as a maximum value because it refers to the phy guaranteed performance. the phy comes out of reset after a delay of no more than 300 s. system designers should consider this value as a minimum value. after de-asserting reset_l, the mac should delay no less than 300 s before accessing the mdio port. t2 reset_l mdio, and so on t1 b3495-01 intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 75 document number: 302875-005 revision date: 27-oct-2005 8.0 register definitions - ieee base registers this chapter includes definitions for the ieee base registers used by the lxt972m transceiver. chapter 9.0, ?register definitions - product-specific registers? includes definitions of additional product-specific lxt972m transceiver registers, which are defined in accordance with the ieee 802.3 standard for adding unique device functions. the lxt972m transceiver register set has multiple 16-bit registers. ? table 40 is a register set listing of the ieee base registers. ? table 41 through table 49 provide bit descriptions of the base registers (address 0 through 8), which are defined in accordance with the ?reconciliation sublayer and media independent interface? and ?physical layer link signaling for 10/100 mbps auto-negotiation? sections of the ieee 802.3 standard. table 40. register set for ieee base registers address register name bit assignments 0 control register see table 41 1 status register #1 see table 42. 2 phy identification register 1 see table 43. 3 phy identification register 2 see table 44. 4 auto-negotiation advertisement register see table 45 5 auto-negotiation link partner base page ability register see table 46. 6 auto-negotiation expansion register see table 47. 7 auto-negotiation next page transmit register see table 48. 8 auto-negotiation link partner next page receive register see table 49. 9 1000base-t/100base-t2 control register not implemented 10 1000base-t/100base-t2 status register not implemented 11 to 14 reserved not implemented 15 extended status register not implemented intel ? lxt972m single-port 10/100 mbps phy transceiver 76 datasheet document number: 302875-005 revision date: 27-oct-2005 table 41 lists control register bits. table 41. control register - address 0, hex 0 bit name description type 1 default 0.15 reset 0 = normal operation 1 = phy reset r/w sc 0 0.14 loopback 0 = disable loopback mode 1 = enable loopback mode r/w 0 0.13 speed selection 0.6 0.13 speed selected r/w note 2 0 0 1 1 0 1 0 1 10 mbps 100 mbps 1000 mbps (not supported) reserved 0.12 auto-negotiation enable 0 = disable auto-negotiation process 1 = enable auto-negotiation process r/w note 2 0.11 power-down 0 = normal operation 1 = power-down r/w 0 0.10 isolate 0 = normal operation 1 = electrically isolate phy from mii r/w 0 0.9 restart auto- negotiation 0 = normal operation 1 = restart auto-negotiation process r/w sc 0 0.8 duplex mode 0 = half-duplex 1 = full-duplex r/w note 2 0.7 collision test 0 = disable col signal test 1 = enable col signal test r/w 0 0.6 speed selection x - 0.6 0.13 speed selected r/w 0 0 0 1 1 0 1 0 1 10 mbps 100 mbps 1000 mbps (not supported) reserved 0.5:0 reserved write as ?0?. ignore on read. r/w 00000 1. r/w = read/write sc = self clearing 2. some bits have their default values determined at reset by hardware configuration pins. for default details for these bits, see section 5.4.4, ?hardware configuration settings? . intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 77 document number: 302875-005 revision date: 27-oct-2005 table 42 lists mii status register bits. table 42. mii status register #1 - address 1, hex 1 bit name description type 1 default 1.15 100base-t4 not supported 0 = phy not able to perform 100base-t4 1 = phy able to perform 100base-t4 ro 0 1.14 100base-x full-duplex 0 = phy not able to perform full-duplex 100base-x 1 = phy able to perform full-duplex 100base-x ro 1 1.13 100base-x half-duplex 0 = phy not able to perform half-duplex 100base-x 1 = phy able to perform half-duplex 100base-x ro 1 1.12 10 mbps full-duplex 0 = phy not able to operate at 10 mbps full-duplex mode 1 = phy able to operate at 10 mbps in full-duplex mode ro 1 1.11 10 mbps half-duplex 0 = phy not able to operate at 10 mbps in half- duplex 1 = phy able to operate at 10 mbps in half-duplex mode ro 1 1.10 100base-t2 full- duplex not supported 0 = phy not able to perform full-duplex 100base-t2 1 = phy able to perform full-duplex 100base-t2 ro 0 1.9 100base-t2 half- duplex not supported 0 = phy not able to perform half-duplex 100base-t2 1 = phy able to perform half-duplex 100base-t2 ro 0 1.8 extended status 0 = no extended status information in register 15 1 = extended status information in register 15 ro 0 1.7 reserved ignore when read. ro 0 1.6 mf preamble suppression 0 = phy cannot accept management frames with preamble suppressed 1 = phy accepts management frames with preamble suppressed ro 0 1.5 auto-negotiation complete 0 = auto-negotiation not complete 1 = auto-negotiation complete ro 0 1.4 remote fault 0 = no remote fault condition detected 1 = remote fault condition detected ro/lh 0 1.3 auto-negotiation ability 0 = phy is not able to perform auto-negotiation 1 = phy is able to perform auto-negotiation ro 1 1.2 link status 0 = link is down 1 = link is up ro/ll 0 1.1 jabber detect 0 = jabber condition not detected 1 = jabber condition detected ro/lh 0 1.0 extended capability 0 = basic register capabilities 1 = extended register capabilities ro 1 1. ro = read only ll = latching low lh = latching high intel ? lxt972m single-port 10/100 mbps phy transceiver 78 datasheet document number: 302875-005 revision date: 27-oct-2005 for table 43 and table 44 , see figure 34 . table 43. phy identification register 1 - address 2, hex 2 bit name description type 1 default 2.15:0 phy id number the phy identifier is composed of bits 3 through 18 of the organizationally unique identifier (oui). ro 0013 hex 1. ro = read only table 44. phy identification register 2 - address 3, hex 3 bit name description type 1 default 3.15:10 phy id number the phy identifier is composed of bits 19 through 24 of the oui. ro 011110 3.9:4 manufacturer?s model number 6 bits containing manufacturer?s part number. ro 001110 3.3:0 manufacturer?s revision number 4 bits containing manufacturer?s revision number. ro for current revision id information, see the specifi- cation update. 1. ro = read only figure 34. phy identifier bit mapping b3504-01 note: the intel oui is 00207b hex 7b phy id register #1 (address 2) = 0013 organizationally unique identifier (qui) phy id register #2 (address 3) manufacturer's model number revision number 50 9 10 15 15 43 0 0 1 1 01 11 1 000011 1 00000 1 0 0 0 0 0 0 0 0 0 0 0 0 a b c r s x 00 0 3 20 00 intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 79 document number: 302875-005 revision date: 27-oct-2005 table 45 lists auto-negotiation advertisement bits. table 45. auto-negotiation advertisement register - address 4, hex 4 bit name description type 1 default 4.15 next page 0 = port has no ability to send multiple pages. 1 = port has ability to send multiple pages. r/w 0 4.14 reserved ignore when read. ro 0 4.13 remote fault 0 = no remote fault. 1 = remote fault. r/w 0 4.12 reserved write as ?0?. ignore on read. r/w 0 4.11 asymmetric pause pause operation defined in ieee 802.3 standard, clause 40 and 27 r/w 0 4.10 pause 0 = pause operation disabled. 1 = pause operation enabled for full-duplex links r/w 0 4.9 100base-t4 0 = 100base-t4 capability is not available. 1 = 100base-t4 capability is available. note: the lxt972m transceiver does not support 100base-t4 but allows this bit to be set to advertise in the auto-negotiation sequence for 100base-t4 operation. an external 100base-t4 transceiver can be switched in if this capability is desired. r/w 0 4.8 100base-tx full-duplex 0 = port is not 100base-tx full-duplex capable. 1 = port is 100base-tx full-duplex capable. r/w note 2 4.7 100base-tx 0 = port is not 100base-tx capable. 1 = port is 100base-tx capable. r/w note 2 4.6 10base-t full-duplex 0 = port is not 10base-t full-duplex capable. 1 = port is 10base-t full-duplex capable. r/w note 2 4.5 10base-t 0 = port is not 10base-t capable. 1 = port is 10base-t capable. r/w note 2 4.4:0 selector field, s<4:0> <00001> = ieee 802.3. <00010> = ieee 802.9 islan-16t. <00000> = reserved for future auto-negotiation development. <11111> = reserved for future auto-negotiation development. note: unspecified or reserved combinations must not be transmitted. r/w 00001 1. r/w = read/write ro = read only 2. some bits have their default values determined at reset by hardware configuration pins. for default details for these bits, see section 5.4.4, ?hardware configuration settings? . intel ? lxt972m single-port 10/100 mbps phy transceiver 80 datasheet document number: 302875-005 revision date: 27-oct-2005 table 46 lists auto-negotiation link partner base page ability bits. table 46. auto-negotiation link partner base page ability register - address 5, hex 5 bit name description type 1 default 5.15 next page 0 = link partner has no ability to send multiple pages. 1 = link partner has ability to send multiple pages. ro 0 5.14 acknowledge 0 = link partner has not received link code word from the lxt972m transceiver. 1 = link partner has received link code word from the lxt972m transceiver. ro 0 5.13 remote fault 0 = no remote fault. 1 = remote fault. ro 0 5.12 reserved ignore when read. ro 0 5.11 asymmetric pause pause operation defined in ieee 802.3 standard, clause 40 and 27. 0 = link partner is not pause capable. 1 = link partner is pause capable. ro 0 5.10 pause 0 = link partner is not pause capable. 1 = link partner is pause capable. ro 0 5.9 100base-t4 0 = link partner is not 100base-t4 capable. 1 = link partner is 100base-t4 capable. ro 0 5.8 100base-tx full-duplex 0 = link partner is not 100base-tx full-duplex capable. 1 = link partner is 100base-tx full-duplex capable. ro 0 5.7 100base-tx 0 = link partner is not 100base-tx capable. 1 = link partner is 100base-tx capable. ro 0 5.6 10base-t full-duplex 0 = link partner is not 10base-t full-duplex capable. 1 = link partner is 10base-t full-duplex capable. ro 0 5.5 10base-t 0 = link partner is not 10base-t capable. 1 = link partner is 10base-t capable. ro 0 5.4:0 selector field s<4:0> <00001> = ieee 802.3. <00010> = ieee 802.9 islan-16t. <00000> = reserved for future auto-negotiation development. <11111> = reserved for future auto-negotiation development. unspecified or reserved combinations must not be transmitted. ro 0 1. ro = read only intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 81 document number: 302875-005 revision date: 27-oct-2005 table 47 lists auto-negotiation expansion bits. table 47. auto-negotiation expansion - address 6, hex 6 bit name description type 1 default 6.15:6 reserved ignore when read. ro 0 6.5 base page this bit indicates the status of the auto-negotiation variable base page. it flags synchronization with the auto-negotiation state diagram, allowing detection of interrupted links. this bit is used only if register bit 16.1 (that is, alternate np feature) is set. 0 = base page = false (base page not received) 1 = base page = true (base page received) ro/lh 0 6.4 parallel detection fault 0 = parallel detection fault has not occurred. 1 = parallel detection fault has occurred. ro/lh 0 6.3 link partner next page able 0 = link partner is not next page able. 1 = link partner is next page able. ro 0 6.2 next page able 0 = local device is not next page able. 1 = local device is next page able. ro 1 6.1 page received this bit is cleared on read. if register bit 16.1 is set, the page received bit is also cleared when either mr_page_rx = false or transmit_disable = true. 1 = indicates a new page is received and the received code word is loaded into register 5 (base pages) or register 8 (next pages) as specified in clause 28 of ieee 802.3. ro/lh 0 6.0 link partner a/n able 0 = link partner is not auto-negotiation able. 1 = link partner is auto-negotiation able. ro 0 1. ro = read only lh = latching high intel ? lxt972m single-port 10/100 mbps phy transceiver 82 datasheet document number: 302875-005 revision date: 27-oct-2005 table 48 lists auto-negotiation next page transmit bits. table 49 lists auto-negotiation link partner next page receive bits. table 48. auto-negotiation next page transmit register - address 7, hex 7 bit name description type 1 default 7.15 next page (np) 0 = last page 1 = additional next pages follow r/w 0 7.14 reserved ignore when read. ro 0 7.13 message page (mp) 0 = register bits 7.10:0 are user defined. 1 = register bits 7.10.0 follow ieee message page format. r/w 1 7.12 acknowledge 2 (ack2) 0 = cannot comply with message 1 = complies with message r/w 0 7.11 toggle (t) 0 = previous value of the transmitted link code word equalled logic one 1 = previous value of the transmitted link code word equalled logic zero r/w 0 7.10:0 message/ unformatted code field if register bits 7.13 = 0, register bits 7.10:0 are user- defined. if register bits 7.13 = 1, register bits 7.10:0 follow ieee message page format. r/w 00000000 001 1. ro = read only. r/w = read/write table 49. auto-negotiation link partner next page receive register - address 8, hex 8 bit name description type 1 default 8.15 next page (np) 0 = link partner has no additional next pages to send 1 = link partner has additional next pages to send ro 0 8.14 acknowledge (ack) 0 = link partner has not received link code word from lxt972m transceiver. 1 = link partner has received link code word from lxt972m transceiver. ro 0 8.13 message page (mp) 0 = register bits 8.10:0 are user defined. 1 = register bits 8.10:0 follow ieee message page format. ro 0 8.12 acknowledge 2 (ack2) 0 = link partner cannot comply with the message 1 = link partner complies with the message ro 0 8.11 toggle (t) 0 = previous value of transmitted link code word equal to logic one 1 = previous value of transmitted link code word equal to logic zero ro 0 8.10:0 message/unformatted code field if register bit 8.13 = 0, register bits 18.10:0 are user defined. if register bit 8.13 = 1, register bits 18.10:0 follow ieee message page format. ro 000000 0000 1. ro = read only. intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 83 document number: 302875-005 revision date: 27-oct-2005 9.0 register definitions - product-specific registers this chapter includes definitions of product-specific lxt972m transceiver registers that are defined in accordance with the ieee 802.3 standard for adding unique device functions. (for definitions of the ieee base registers used by the lxt972m transceiver, see chapter 8.0, ?register definitions - ieee base registers? .) ? table 50 lists the register set of the product-specific registers. ? table 51 through table 56 provide bit descriptions of the product-specific registers (address 17 through 30). table 50. register set for product-specific registers address register name bit assignments 16 port configuration register see table 51 17 status register #2 see table 52 18 reserved 19 status change register see table 53 20 led configuration register see table 54 21 reserved 22-25 reserved 26 digital configuration register see table 55 27 reserved 28 reserved 29 reserved 30 transmit control register see table 56 31 reserved intel ? lxt972m single-port 10/100 mbps phy transceiver 84 datasheet document number: 302875-005 revision date: 27-oct-2005 table 51 lists configuration bits. table 51. configuration register - address 16, hex 10 bit name description type 1 default 16.15 reserved write as ?0?. ignore on read. r/w 0 16.14 force link pass 0 = normal operation 1 = force link pass r/w 0 16.13 transmit disable 0 = normal operation 1 = disable twisted pair transmitter r/w 0 16.12 bypass scrambler (100base-tx) 0 = normal operation 1 = bypass scrambler and descrambler r/w 0 16.11 reserved write as ?0?. ignore on read. r/w 0 16.10 jabber (10base-t) 0 = normal operation 1 = disable jabber correction r/w 0 16.9 sqe (10base-t) 0 = disable heart beat 1 = enable heart beat r/w 0 16.8 tp loopback (10base-t) 0 = normal operation 1 = disable tp loopback during half-duplex operation r/w 0 16.7 crs select (10base-t) 0 = normal operation 1 = crs deassert extends to rx_dv deassert r/w 1 16.6 reserved write as ?0?. ignore on read. r/w 0 16.5 pre_en preamble enable. 0 = set rx_dv high coincident with sfd. 1 = set rx_dv high and rxd = preamble when crs is asserted. note: preamble is always enabled in 100 mbps operation. r/w 0 16.4:3 reserved write as ?0?. ignore on read. r/w 00 16.2 reserved write as ?0?. ignore on read. r/w 0 16.1 alternate np feature 0 = disable alternate auto negotiate next page feature. 1 = enable alternate auto negotiate next page feature. this bit enables or disables the register bit 6.5 capability. r/w 0 16.0 reserved write as ?0?. ignore on read. r/w 0 1. r/w = read /write intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 85 document number: 302875-005 revision date: 27-oct-2005 table 52 lists register #2 status bits. table 52. status register #2 - address 17, hex 11 bit name description type 1 default 17.15 reserved always 0. ro 0 17.14 10/100 mode 0 = lxt972m transceiver is not operating 100base-tx mode. 1 = lxt972m transceiver is operating in 100base-tx mode. ro 0 17.13 transmit status 0 = lxt972m transceiver is not transmitting a packet. 1 = lxt972m transceiver is transmitting a packet. ro 0 17.12 receive status 0 = lxt972m transceiver is not receiving a packet. 1 = lxt972m transceiver is receiving a packet. ro 0 17.11 collision status 0 = no collision. 1 = collision is occurring. ro 0 17.10 link 0 = link is down. 1 = link is up. ro 0 17.9 duplex mode 0 = half-duplex. 1 = full-duplex. ro 0 17.8 auto-negotiation 0 = lxt972m transceiver is in manual mode. 1 = lxt972m transceiver is in auto-negotiation mode. ro 0 17.7 auto-negotiation complete 0 = auto-negotiation process not completed. 1 = auto-negotiation process completed. this bit is valid only when auto negotiate is enabled. the value is equivalent to the value of register bit 1.5. ro 0 17.6 reserved always 0. ro 0 17.5 polarity 0 = polarity is not reversed. 1 = polarity is reversed. note: polarity is not a valid status in 100 mbps mode. ro 0 17.4 pause 0 = the lxt972m transceiver is not pause capable. 1 = the lxt972m transceiver is pause capable. r0 17:3 error 0 = no error occurred 1 = error occurred (remote fault, jabber, parallel detect fault) note: the register bit is cleared when the registers that generate the error condition are read. ro 0 17:2 reserved always 0. ro 0 17:1 reserved always 0. ro 0 17.0 reserved always 0. ro 0 1. ro = read only. r/w = read/write intel ? lxt972m single-port 10/100 mbps phy transceiver 86 datasheet document number: 302875-005 revision date: 27-oct-2005 table 53 lists status change bits. table 53. status change register - address 19, hex 13 bit name description type 1 default 19.15:9 reserved ignore on read. ro n/a 19.8 reserved ignore on read. ro 0 19.7 andone auto-negotiation status 0 = auto-negotiation has not completed. 1 = auto-negotiation has completed. ro/ sc n/a 19.6 speedchg speed change status 0 = a speed change has not occurred since last reading this register. 1 = a speed change has occurred since last reading this register. ro/ sc 0 19.5 duplexchg duplex change status 0 = a duplex change has not occurred since last reading this register. 1 = a duplex change has occurred since last reading this register. ro/ sc 0 19.4 linkchg link status change status 0 = a link change has not occurred since last reading this register. 1 = a link change has occurred since last reading this register. ro/ sc 0 19.3 reserved ignore on read. ro 0 19.2 reserved ignore on read. ro 0 19.1 reserved ignore on read. ro 0 19.0 reserved ignore on read. ro 0 1. r/w = read/write, ro = read only, sc = self clearing. intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 87 document number: 302875-005 revision date: 27-oct-2005 table 54 lists led configuration bits. table 54. led configuration register - address 20, hex 14 (sheet 1 of 2) bit name description type 1 default 20.15:12 led1 programming bits 0000 = display speed status (continuous, default) 0001 = display transmit status (stretched) 0010 = display receive status (stretched) 0011 = display collision status (stretched) 0100 = display link status (continuous) 0101 = display duplex status (continuous) 0110 = unused 0111 = display receive or transmit activity (stretched) 1000 = test mode - turn led on (continuous) 1001 = test mode - turn led off (continuous) 1010 = test mode - blink led fast (continuous) 1011 = test mode - blink led slow (continuous) 1100 = display link and receive status combined 2 (stretched) 3 1101 = display link and activity status combined 2 (stretched) 3 1110 = display duplex and collision status combined 4 (stretched) 3 1111 = unused r/w 0000 20.11:8 led2 programming bits 0000 = display speed status 0001 = display transmit status 0010 = display receive status 0011 = display collision status 0100 = display link status (default) 0101 = display duplex status 0110 = unused 0111 = display receive or transmit activity 1000 = test mode - turn led on 1001 = test mode - turn led off 1010 = test mode - blink led fast 1011 = test mode - blink led slow 1100 = display link and receive status combined 2 (stretched) 3 1101 = display link and activity status combined 2 (stretched) 3 1110 = display duplex and collision status combined 4 (stretched) 3 1111 = unused r/w 0100 1. r/w = read /write. ro = read only. lh = latching high 2. link status is the primary led driver. the led is asserted (solid on) when the link is up. the secondary led driver (receive or activity) causes the led to change state (blink). activity causes the led to blink, regardless of the link status. 3. combined event led settings are not affected by pulse stretch register bit 20.1. these display settings are stretched regardless of the value of 20.1. 4. duplex status is the primary led driver. the led is asserted (solid on) when the link is full-duplex. collision status is the secondary led driver. the led changes state (blinks) when a collision occurs. 5. values are approximations. not guaranteed or production tested. intel ? lxt972m single-port 10/100 mbps phy transceiver 88 datasheet document number: 302875-005 revision date: 27-oct-2005 table 55 lists digital configuration bits for the lxt972m transceiver. 20.7:4 led3 programming bits 0000 = display speed status 0001 = display transmit status 0010 = display receive status (default) 0011 = display collision status 0100 = display link status 0101 = display duplex status 0110 = unused 0111 = display receive or transmit activity 1000 = test mode- turn led on 1001 = test mode- turn led off 1010 = test mode- blink led fast 1011 = test mode- blink led slow 1100 = display link and receive status combined 2 (stretched) 3 1101 = display link and activity status combined 2 (stretched) 3 1110 = display duplex and collision status combined 4 (stretched) 3 1111 = unused r/w 0010 20.3:2 ledfreq 5 00 = stretch led events to 30 ms. 01 = stretch led events to 60 ms. 10 = stretch led events to 100 ms. 11 = reserved. r/w 00 20.1 pulse- stretch 0 = disable pulse stretching of all leds. 1 = enable pulse stretching of all leds. r/w 1 20.0 reserved write as ?0?. ignore on read. r/w 0 table 54. led configuration register - address 20, hex 14 (sheet 2 of 2) bit name description type 1 default 1. r/w = read /write. ro = read only. lh = latching high 2. link status is the primary led driver. the led is asserted (solid on) when the link is up. the secondary led driver (receive or activity) causes the led to change state (blink). activity causes the led to blink, regardless of the link status. 3. combined event led settings are not affected by pulse stretch register bit 20.1. these display settings are stretched regardless of the value of 20.1. 4. duplex status is the primary led driver. the led is asserted (solid on) when the link is full-duplex. collision status is the secondary led driver. the led changes state (blinks) when a collision occurs. 5. values are approximations. not guaranteed or production tested. table 55. digital configuration register - address 26, hex 1a bit name description type 1 default 26.15:12 reserved write as ?0?. ignore on read. r/w 0000 26.11 mii drive strength mii drive strength 0 = normal mii drive strength 1 = increase mii drive strength r/w 0 26.10 reserved write as ?0?. ignore on read. r/w 0 26.9 show symbol error show symbol error 0 = normal mii_rxer 1 = 100base-x error signal to mii_rxer r/w 0 26.8:0 reserved write as ?0?. ignore on read. ro 00000000 0 1. r/w = read /write, ro = read only intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 89 document number: 302875-005 revision date: 27-oct-2005 table 56 lists transmit control bits. table 56. transmit control register - address 30, hex 1e bit name description type 2 default 30.15:13 reserved write as ?0?. ignore on read. r/w 000 30.12 transmit low power transmit low power 0 = normal transmission. 1 = forces the transmitter into low power mode. also forces a zero-differential transmission. r/w 0 30.11:10 port rise time control 1 port rise time control 00 = 3.0 ns (default) 01 = 3.4 ns 10 = 3.9 ns 11 = 4.4 ns r/w 00 30.9:0 reserved ignore on read. r/w 0000000 000 1. values are approximations and may vary outside indicated values based upon implementation loading conditions. not guaranteed. 2. r/w = read/write 3. latch state during reset is based on the state of hardware configuration pins at reset_l. intel ? lxt972m single-port 10/100 mbps phy transceiver 90 datasheet document number: 302875-005 revision date: 27-oct-2005 10.0 intel ? lxt972m transceiver package specifications figure 35. intel ? lxt972m transceiver lqfp package specifications d d 1 a 1 a 2 l a b l 1 3 3 e e 1 e / 2 e 48-pin low-profile quad flat pack part number lxt972m - temperature range (0oc to +70oc) note: the package figure is generic and used only to demonstrate package dimensions. d d 1 e e 1 b3813-01 3x c0.30 (in mm) x 45 c0.55 (in mm) x 45 5.500 ref (in mm) 5.500 ref (in mm) pin 1 note: the 5.500 ref measure i s from the center of first pin to the center of last pin. dim millimeters min max a?1.60 a 1 0.05 0.15 a 2 1.35 1.45 b0.170.27 d8.809.20 d 1 6.90 7.10 e8.809.20 e 1 6.90 7.10 e0.50 bsc 1 l0.450.75 l 1 1.00 ref 3 11 o 13 o 0 o 7 o 1. basic spacing between centers intel ? lxt972m single-port 10/100 mbps phy transceiver datasheet 91 document number: 302875-005 revision date: 27-oct-2005 10.1 top label markings figure 36 shows a sample lqfp package for the lxt972m transceiver. note: in contrast to the pb-free (rohs-compliant) lqfp package, the non-rohs-compliant package does not have the ?e3? symbol in the last line of the package label. figure 37 shows a sample pb-free (rohs-compliant) lqfp package for the lxt972m transceiver. figure 36. sample lqfp package - intel ? lxt972m transceiver pin 1 xxxxxxxx part number fpo number dj972ma4 c m ? yy blank line year b5294-01 figure 37. sample pb-free (rohs-compliant) lqfp package - intel ? lx972m transceiver pin 1 xxxxxxxx part number fpo number wj972ma4 c m ? yy blank line pb-free indication e3 year b5295-01 intel ? lxt972m single-port 10/100 mbps phy transceiver 92 datasheet document number: 302875-005 revision date: 27-oct-2005 11.0 product ordering information table 57 lists product ordering information for the lxt972m transceiver. figure 38 shows an order matrix with sample information for ordering an lxt972m transceiver. table 57. product ordering information number revision package type pin count rohs compliant djlxt972mlc.a4 a4 lqfp 48 no wjlxt972mlc.a4 a4 lqfp 48 yes figure 38. order matrix for intel ? lxt972m transceiver dj c 972m l lxt a4 product revision xn = 2 alphanumeric characters temperature range a = ambient (0 ? 55 0 c) c = commercial (0 ? 70 0 c) e = extended (-40 ? 85 0 c) internal package designator l = lqfp p = plcc n = dip q = pqfp h = qfp t = tqfp b = bga c = cbga e = tbga k = hsbga (bga with heat slug product code xxxxx = 3-5 digit alphanumeric ixa product prefix lxt = phy layer device ixe = switching engine ixf = formatting device (mac/framer) ixp = network processor intel package designator b4863-02 |
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